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News Release from: Cadence Design Systems | Subject: Virtuoso NeoCircuit
Edited by the Electronicstalk Editorial
Team on 13 June 2005
Reusable IP accelerates Oki's analogue
design
Oki Electric has achieved five times faster design turnaround time for its analogue blocks than with its previous design methodology by using Cadence Virtuoso NeoCircuit technology.
Oki Electric has achieved five times faster design turnaround time for its analogue blocks than with its previous design methodology and has successfully completed 30 reusable analogue intellectual property (IP) designs using Cadence Virtuoso NeoCircuit technology "Cadence's Virtuoso NeoCircuit technology has become a key component of Oki's analogue IP creation", said Ichiro Yamamoto, Senior Manager, Design System Department in the LSI Design Division of Oki Electric's Silicon Solutions Company
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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"We are proud to announce that we have established a new design culture based on Virtuoso NeoCircuit with our proprietary IP templates".
"This Cadence technology allows us to compete more effectively with other leading manufacturers in this market segment".
Oki's designers were looking to reuse the analogue IP they had already created without having to manually repeat design work.
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The use of this fully tested IP reduced the need for - and, therefore, time spent on - expensive verification cycles and silicon respins.
This had the added benefit of allowing designers to focus on their core competencies.
Since adopting Cadence's NeoCircuit technology in December 2003, Oki has been using it to design analogue circuits for personal mobile market-use LSIs (large scale integrated circuits), sound generator LSIs, memory LSIs including P2ROM, DRAM and FeRAM, flat panel display (FPD) driver LSIs for TFT-LCDs and OLEDs etc.
With this technology, the company has been able to achieve five times faster design turnaround time than with its previous design methodology.
Internal Oki testing has proven that the quality of the analogue circuits designed using NeoCircuit is much higher than the circuits designed from scratch.
Cadence Virtuoso NeoCircuit technology enables designers to rapidly size their circuit to meet performance specifications.
The technology provides design teams the ability to predict silicon performance, improve yield and achieve improved design accuracy.
Virtuoso NeoCircuit is an integral part of a front-to-back automated rapid analogue design (RAD) flow and provides circuit designers with a fast efficient methodology for generating analogue IP, all the way from schematic entry through to physical layout.
analogue circuitry is challenging to design, and analogue content is extremely sensitive to process variations.
These challenges can adversely impact chip yields.
Cadence Virtuoso NeoCircuit technology speeds SoC and analogue/mixed-signal design and improves quality by providing design exploration, design centring and circuit and layout optimisation early in the design cycle.
This enables designers to optimise circuit specifications while taking into account manufacturing variations.
The net result is higher-performance designs with improved yield in less time.
Moreover, circuits created with this unique design methodology become analogue IP that designers can reuse and retarget to new processes, speeding time to market.
"Cadence is very pleased that Oki has successfully established its analogue design environment in less than a year and, in the process, created over 30 analogue IP designs based on the Cadence Virtuoso NeoCircuit technology", said Felicia James, Vice President and General Manager, Cadence Virtuoso Custom Design Platform.
"This success is proof of Oki's advanced analogue design innovation".
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