Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter and Allegro
Edited by the Electronicstalk Editorial
Team on 13 June 2005
TSMC integrates nanometre design
platforms
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's latest reference flow.
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 6.0 This reference flow, which supports designs targeting TSMC's Nexsys 65nm process technologies, includes innovative Cadence software for power optimisation and analysis, design for manufacturing (DFM), chip-package integration, and design for test (DFT)
This article was originally published on Electronicstalk on 10 Jun 2004 at 8.00am (UK)
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This latest milestone in the ongoing design chain collaboration between the two companies delivers an RTL-to-package reference flow to accelerate time to volume for high-performance and low-power designs.
It delivers a comprehensive methodology to address complex design issues at 90 and 65nm, such as tight manufacturing parameters, an exponential increase in leakage power, and new extraction requirements.
Within Reference Flow 6.0, Cadence technologies address these key issues by performing concurrent routing and dual via insertion, supporting aggressive leakage power reduction strategies and optimising package performance and cost.
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"Reference Flow 6.0's Cadence track incorporates Cadence technologies to lower the entry barrier for designers targeting TSMC's advanced processes", said Ed Wan, Senior Director of Design Service Marketing at TSMC.
"We collaborated closely with Cadence to meet the complex requirements that designers are facing at 65nm, which include power management, chip and package co-design, and manufacturing".
"Our collaboration with leaders throughout the design chain provides silicon-validated design solutions necessary for market success", said Pankaj Mayor, Group Director of Business Development for Industry Alliances at Cadence.
"We focus on correlating models, software and IP with silicon by creating test chips such as the low-power test chip with TSMC through the Silicon Design Chain Initiative earlier this year".
"Leveraging those results through TSMC Reference Flow 6.0 improves the probability of nanometre design success".
TSMC Reference Flow 6.0 incorporates key elements of the Cadence Encounter platform - voltage domain-aware technologies from Reference Flow 5.0 - to create power-gated paths and dynamic voltage scaling.
Designers can use these technologies to design with multiple supply voltages and power domains, leakage power and decoupling capacitance optimisation, automatic power grid generation, and dynamic voltage (IR) drop analysis with actual IC package load models.
The Encounter platform provides a scalable methodology to go from a non-power-domain design to power-domain-based designs.
Elements of the Encounter platform within Reference Flow 6.0 include Encounter RTL Compiler global synthesis, Encounter Test, SoC Encounter Global Physical Synthesis (GPS), Cadence extraction technology, VoltageStorm Dynamic Gate power rail analysis and CeltIC Nanometre Delay Calculator (NDC), which work together to deliver high quality of silicon (QoS), improved timing closure, and reduced area.
Cadence SoC Encounter Global Physical Synthesis (GPS), which is included in Reference Flow 6.0, brings to the IC design process critical manufacturing issues such as wire spreading, double-cut via optimisation, and metal fill.
SoC Encounter GPS can automatically insert metal fill into a placed and routed design to achieve a metal density within the range recommended by TSMC design rules.
It also enables automated wire-spreading and double-cut (dual) via insertion, which positively impact yield.
Routability, timing, and IR drop are major concerns for chip and package co-design and integration.
To help optimise chip and package design flows, TSMC features the Cadence Allegro system interconnect platform in Reference Flow 6.0.
Allegro Package Designer can help achieve design of high-performance interconnect across the IC, package, and PCB domains.
The Allegro platform comprises a common constraint-driven flow across design entry, including extraction of package parasitics and inclusion of these package effects into the IC-level timing and static and dynamic IR drop modelling environments.
Within TSMC Reference Flow 6.0, the Allegro platform addresses 65nm and below design challenges, such as flip-chip interconnect density, gigahertz signal integrity and clean power delivery of low-voltage, high power consumption chips.
Encounter Test has been validated by TSMC in Reference Flow 6.0 to address DFT and delay test ATPG.
Increasing design complexity and nanometre-scale geometries make manufacturing test critical for IC success.
Creating an effective, full-chip test architecture, minimising test cost, maximising product quality, and quickly ramping yield are major design challenges.
Encounter Test addresses these issues within the TSMC reference flow with the industry's most advanced, comprehensive test solution, including DFT, delay test, compression and diagnostics.
TSMC Reference Flow 6.0 is available through the company's customer website.
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