Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter RTL Compiler
Edited by the Electronicstalk Editorial
Team on 17 June 2005
Compiler speeds image processor to
tape-out
Nethra Imaging has successfully taped out its first product, the NI-2050 image processor designed for mobile handset applications, using Cadence Encounter RTL Compiler synthesis.
Nethra Imaging has successfully taped out its first product, the NI-2050 image processor designed for mobile handset applications, using Cadence Encounter RTL Compiler synthesis The use of Encounter RTL Compiler helped Nethra achieve a very short design cycle with no room for error, first-time working silicon, the smallest possible die sise, low cost and the least possible power dissipation
This article was originally published on Electronicstalk on 19 Feb 2004 at 8.00am (UK)
Related stories
VHDL support speeds silicon synthesis
Encounter RTL Compiler synthesis is a key component of the Encounter digital IC design platform and a critical step in the fastest route to superior silicon.
Agere accepts Encounter netlists
Agere Systems now accepts netlists produced by Cadence Encounter RTL Compiler synthesis for implementation in its ASIC design centres.
ASIC designers achieved these goals in record time because Encounter RTL Compiler provided an efficient and accurate netlist for timing closure.
"Encounter RTL Compiler was an integral part of our design flow", said Ravi Bhatnagar, Senior Vice President of Engineering at Nethra.
"Our engineers have found the tool to be fast and powerful".
Further reading
RTL compiler is a qualified SoC success
PalmChip Corp has qualified the Cadence Encounter RTL Compiler for implementation of its popular AcurX SoC platform.
Compiler cuts SoC power and area for Oki
Oki has successfully taped out a chip for its uPlat SoC design platform with the new low-power capability of Cadence Encounter RTL Compiler synthesis.
"The synthesis results were up to our expectation, and it helped us save power and area".
"RTL Compiler, along with other tools in the flow, helped us achieve first-time working silicon".
Encounter RTL Compiler's global synthesis approach enables simultaneous optimisation of timing, power, and area in a top-down run.
This produces a netlist that goes through place and route more cleanly with better results.
"We were able to incorporate Encounter RTL Compiler into our flow very quickly", said Deepak Tripathi, Nethra's ASIC Design Manager.
"It was able to quickly and easily synthesise our design top down with multiple clock domains".
"RTL Compiler also has a very impressive set of features to support low-power design and design-for-test techniques".
"The quality of the netlist was such that we were able to close timing with place and route in record time".
"We received excellent support both during initial adoption and while customising the synthesis flow to best suit our needs".
"RTL Compiler's flexibility and capabilities are very impressive".
Interconnect related parameters in nanometre designs require a new metric for synthesis results that includes performance, area, and power measured with wires.
Cadence defines this as quality of silicon (QoS).
Cadence Encounter RTL Compiler's global synthesis enables designers to achieve the highest QoS in less time and with less effort.
"We are excited that Encounter RTL Compiler played a significant role in enabling Nethra Imaging to meet its design goals and successfully sample its first product", said Dr Chi-Ping Hsu, Corporate Vice President at Cadence.
"This is another proof point of how Encounter RTL Compiler enables customers to implement smaller, faster and cooler chips in less time".
During the last 12 months, 75 new customers adopted Encounter RTL Compiler.
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
