RTL compiler speeds LCD controller to tapeout

Seiko Epson Corp of Japan has doubled productivity in the production tapeout of a high-volume LCD controller chip using Cadence Encounter RTL Compiler synthesis.

Seiko Epson Corp of Japan has doubled productivity in the production tapeout of a high-volume LCD controller chip using Cadence Encounter RTL Compiler synthesis.

A 50% reduction in synthesis runtime, top-down synthesis and a clean netlist with the ability to route with no detours all contributed to timing closure and a substantial improvement in time to market for Epson.

Encounter RTL Compiler, part of the Encounter digital IC design platform, shortens design turnaround time by delivering superior quality of silicon (QoS) through physical design.

In addition to fast runtimes, Encounter RTL Compiler offers a true top-down synthesis methodology to avoid the lengthy manual effort of block-level integration.

Epson is a global leader in electronics devices including semiconductors and LCD displays, as well as imaging products including printers and projectors.

"LCD controllers are one of the most important products for Epson's semiconductor business, and design turnaround time is the most critical factor in maintaining our leadership position in this highly competitive market", said Kanji Aoki, Manager of the IC Design Technology Department at Epson.

"With its leading-edge technology, Encounter RTL Compiler helped us meet the design schedule".

"Our designers will continue to follow the top-down synthesis method enabled by Encounter RTL Compiler to maximise our time-to-market advantages".

Interconnect-related parameters in nanometre designs require a new metric for synthesis results that includes performance, area and power measured with wires.

Cadence defines this as quality of silicon.

Cadence Encounter RTL Compiler's global synthesis enables designers to achieve the highest QoS in less time and with less effort.

"We are excited that Encounter RTL Compiler played a significant role in enabling Epson to meet its design goals and successfully tape out a key high-volume production chip", said Dr Chi-Ping Hsu, Corporate Vice President at Cadence.

"This is another proof point of how Encounter RTL Compiler enables customers like Epson to design smaller and faster chips more economically and in less time".

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