Product category:
Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 22 July 2005
Compiler synthesis proves popular in
Japan
Canon has adopted Encounter RTL Compiler for its ASIC designs, further increasing momentum of RTL Compiler synthesis in Japan.
Canon has adopted Encounter RTL Compiler for its ASIC designs, further increasing momentum of RTL Compiler synthesis in Japan The improvements in area, performance and power delivered by Encounter RTL Compiler make designs more competitive, and these benefits have accelerated its adoption by customers worldwide
This article was originally published on Electronicstalk on 19 Feb 2004 at 8.00am (UK)
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During the last 12 months, over 80 new customers have adopted Encounter RTL Compiler.
"The evaluations of our previous ASIC designs using Encounter RTL Compiler have shown us consistent benefits", said Yasuhiro Tani, Senior General Manager, SOC Design Centre, Platform Technology Development Headquarters at Canon, Japan.
"We have adopted Encounter RTL Compiler for future tapeouts because of its proven ability to increase chip performance, reduce power, reduce turnaround time and increase productivity".
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Ricoh Company has successfully taped out a 3-million-gate chip ahead of schedule and with reduced gate count using the Cadence Encounter digital IC design platform, including RTL Compiler synthesis.
"We will now make support for Encounter RTL Compiler a requirement for our ASIC vendors".
Encounter RTL Compiler global synthesis has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route.
This ability to produce smaller, faster and cooler chips in less time has increased customer competitiveness and reduced overall costs.
In order to support increased demand and usage of RTL Compiler by customers, a number of leading ASIC vendors have qualified Encounter RTL compiler for their customers.
"The benefits of the RTL Compiler's global synthesis technology will allow designers to significantly reduce design cost and improve time to market", said Satoshi Andou, General Manager, Design Methodology Development Division, Electronic Devices Business Group at Fujitsu.
"Fujitsu will support Encounter RTL Compiler for our internal and external ASIC customers".
"As a result of increasing customer usage and its ability to produce high-quality netlists for implementation, NEC Electronics has adopted Encounter RTL Compiler as part of our ASIC design flow and will support Encounter RTL Compiler for synthesis", said Kazu Yamada, Associate Vice President, Technology Foundation Development Operation Unit from NEC Electronics.
"We want to ensure that our customers are enabled to take the most out of our ASIC offering to achieve their design goals in the shortest time possible".
"Our evaluation of Cadence Encounter RTL Compiler for synthesis of ASIC designs has demonstrated to us its value for producing optimised netlists for large designs and meet design goals for performance and die size", said Shin-ichi Imai, Senior Manager, System LSI Design Dept.
System LSI Division I at Toshiba.
"As a result, we will support RTL Compiler for production tapeouts".
Interconnect related parameters in nanometre designs require a new metric for synthesis results that includes performance, area, and power measured with wires.
Cadence defines this as quality of silicon (QoS).
Cadence Encounter RTL Compiler's global synthesis enables designers to achieve the highest QoS in less time and with less effort.
"Achieving this level of customer adoption in such a short time is a testament to the superiority of Cadence's patented global synthesis approach", said Dr Chi-Ping Hsu, Corporate Vice President at Cadence.
"Encounter RTL Compiler is now being successfully used in production by companies throughout the world to achieve a competitive advantage via the fastest path to the highest QoS".
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