Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter RTL Compiler
Edited by the Electronicstalk Editorial
Team on 02 August 2005
Compiler helps cut consumer IC down to
size
Sunplus Technology Company of Taiwan has achieved an important production tapeout of a reduced-die-size consumer-electronics chip using Cadence technology.
Sunplus Technology Company of Taiwan has achieved an important production tapeout of a reduced-die-size consumer-electronics chip using Cadence technology Using Cadence Encounter RTL Compiler global synthesis, Sunplus completed the DVD chip in just one month
This article was originally published on Electronicstalk on 19 Feb 2004 at 8.00am (UK)
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Encounter RTL Compiler, part of the Encounter digital IC design platform, enabled Sunplus to shrink the die size of the 2-million-gate design to meet the area constraint for the whole chip while also speeding the physical implementation process.
According to Sunplus, Encounter RTL Compiler created a small enough design that engineers could meet their die size requirement with margin to spare.
This extra margin helped speed physical implementation and reduce the project schedule to one month.
As a result, Sunplus was able to cut its project costs for this high-volume DVD chip and get it to market more quickly.
"Sunplus participates in the highly competitive consumer electronics market".
"We are always looking for a competitive edge", said Chih-Hao Kung, VP of Research and Development at Sunplus.
"We found that Encounter RTL Compiler gave us both cost and time-to-market advantages that measurably impact our bottom line".
Encounter RTL Compiler has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route.
Cadence defines this metric as quality of silicon (QoS).
This ability to produce smaller, faster and cooler chips in less time has increased customer competitiveness and reduced overall costs.
"This successful Encounter RTL Compiler tapeout at Sunplus is another example of how Cadence's patented global synthesis technology can help increase customer success in a highly competitive market space", said Dr Chi-Ping Hsu, Corporate Vice President at Cadence.
"Encounter RTL Compiler is now being successfully used in production by companies worldwide to create smaller, faster, and lower power designs in a very short time".
Encounter RTL Compiler has been used in production by more than 100 customers worldwide for competitive markets in consumer, communications, computer, networking, graphics and SoC designs.
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