Product category:
Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 05 October 2005
Comit gains greater access to Cadence
technology
Comit Systems has expanded its access to Cadence technology, and has standardised on Encounter RTL Compiler global synthesis, part of the Encounter digital IC design platform.
Comit Systems has expanded its access to Cadence technology, and has standardised on Encounter RTL Compiler global synthesis, part of the Encounter digital IC design platform, to improve productivity and speed of implementation Comit Systems provides turnkey contract engineering services for electronic-product development through the design of chips, boards, software and systems, using the latest enabling technologies and tools
This article was originally published on Electronicstalk on 19 Feb 2004 at 8.00am (UK)
Related stories
VHDL support speeds silicon synthesis
Encounter RTL Compiler synthesis is a key component of the Encounter digital IC design platform and a critical step in the fastest route to superior silicon.
Agere accepts Encounter netlists
Agere Systems now accepts netlists produced by Cadence Encounter RTL Compiler synthesis for implementation in its ASIC design centres.
Comit, a long-time Cadence partner, has used the Encounter platform to tape out several chips, all of which were successful on the first pass.
Recently Comit significantly increased its access to Cadence technologies for synthesis and physical implementation.
Comit's experience with Encounter RTL Compiler showed that the company can reduce the time from RTL to netlist from a few days to a few hours by synthesising a multi-million-gate chip with DFT top-down, requiring only chip-level constraints.
Further reading
RTL compiler is a qualified SoC success
PalmChip Corp has qualified the Cadence Encounter RTL Compiler for implementation of its popular AcurX SoC platform.
Compiler cuts SoC power and area for Oki
Oki has successfully taped out a chip for its uPlat SoC design platform with the new low-power capability of Cadence Encounter RTL Compiler synthesis.
"At Comit we are always looking for technologies that deliver superior results and speed our time to results", said Venkat Iyer, Vice President of Engineering at Comit.
"Encounter RTL Compiler is a modern tool that presents non-proprietary intermediate representation formats for better flow analysis".
"We can now do area, power or speed optimisation and target it to a particular area of design, as dictated by our customers' needs".
"As a design house, we value these features that enhance our competitiveness".
"Equally important was the fact that Cadence understood our business model and made it easy for us to do business with the company".
Encounter RTL Compiler global synthesis has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route.
Cadence defines this metric as quality of silicon (QOS).
This ability to produce smaller, faster and cooler chips in less time has increased customer competitiveness and reduced overall costs".
"Comit has been a leading-edge design house in Silicon Valley for a long time and we view the company as an important partner", said Dr Chi-Ping Hsu, Corporate Vice President at Cadence".
"As it recently expanded its access to Cadence solutions, we were impressed with the speed with which Comit integrated RTL Compiler with little or no support".
Encounter RTL Compiler has been used in production by more than 100 customers worldwide for competitive markets in consumer, communications, computer, networking, graphics, and SOC designs.
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page

