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Design Services
News Release from: Cadence Design Systems | Subject: PowerPC design services
Edited by the Electronicstalk Editorial
Team on 29 September 2005
Help at hand for PowerPC-based SoC
design
New services will aid SoC designers embedding PowerPC cores, including silicon validation of a new custom-synthesised design approach.
Cadence Design Systems has come up with a comprehensive set of services for SoC designers embedding PowerPC cores, including silicon validation of a new custom-synthesised design approach The new approach results in up to a 30% increase in processor speed and a 40% reduction in chip area
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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Developed in close collaboration with IBM, the custom-synthesised approach provides a new schedule-performance tradeoff point for performance-minded SoC designers embedding PowerPC cores.
It advances PowerPC portability in markets such as consumer and networking, where processor speed and area results achievable with a full-synthesis approach may fall short, yet the performance of a full-custom approach is prohibited by time-to-market constraints.
"The PowerPC architecture is critical to the computing and gaming markets and is rapidly expanding into broader applications, including emerging markets in SoC", said Tom Reeves, Vice President of Semiconductor Products and Solutions at IBM.
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"We expect this new custom-synthesised approach from Cadence, coupled with their expertise in design services, to help drive increased market adoption of the PowerPC architecture".
compared with a full-synthesis approach, the Cadence custom-synthesised approach achieves a 20 to 30% increase in processor speed while reducing chip area by 40%.
Cadence Engineering Services achieves these results using Cadence's Virtuoso custom design platform to do full-custom design on the eight to 10 design blocks that most affect timing, power and area, such as the demanding CAMRAMs on the PowerPC 440 core.
The remaining blocks are designed using Cadence's RTL Compiler synthesis, which has provided market-leading results for cycle time and chip real estate in PowerPC applications.
"SoC designers select the PowerPC as their processor core for its high performance, small core area and low power features".
"Now they can have it ported to their choice of fab with no sacrifice in these features", said Tim Henricks, Vice President for Cadence Engineering Services.
"Through collaboration with IBM, we have developed PowerPC porting capabilities superior to straight synthesis approaches that provide the performance these designers demand".
The custom-synthesised approach for PowerPC designers was validated in silicon by using a PowerPC 440 on the TSMC 130-LV manufacturing process.
Cadence is taking a comprehensive approach to meeting the needs of PowerPC designers.
Because software development consumes the most schedule time in complex SoCs with powerful microprocessors, Cadence is offering coverification services based on the Palladium emulation platform.
This helps reduce time to market and schedule risk at the system level by allowing design teams to develop software in parallel with the SoC design.
"L-3 has experienced successful results running the IBM PowerPC with Cadence's Palladium emulator", said Jim Grace, Vice President of Business Development, L-3 Communications, Interstate Electronics Corporation.
"We are looking forward to working with IBM and Cadence as they continue developing preferred solutions for the PowerPC".
Cadence is a founding member of Power.org, an open standards community that will help IC designers develop system-on-chips (SoCs) using the IBM PowerPC Architecture.
Power.org is dedicated to promoting the IBM PowerPC architecture as the preferred open-standard hardware-development platform for electronic systems for markets such as consumer electronics, networking, storage, military and automotive.
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