Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Incisive
Edited by the Electronicstalk Editorial
Team on 26 October 2005
Functional verification takes tailored
approach
Cadence Design Systems has repackaged its Incisive functional verification platform, including full solutions with tailored and integrated products coupled with methodologies for unique segment needs.
Cadence Design Systems has repackaged its Incisive functional verification platform, including full solutions with tailored and integrated products coupled with methodologies for unique segment needs The product families add additional support for multiple languages optimised for each specialist, including the most powerful, yet lowest risk, SystemVerilog-based offering
This article was originally published on Electronicstalk on 26 Feb 2003 at 8.00am (UK)
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The three-tiered approach provides Cadence customers with optimal solutions tailored to specific levels of verification complexity.
The top tier is the Incisive Enterprise family of solutions for multi-specialist SoC and system development teams.
The family features enterprise-level verification process automation (VPA) and management capabilities.
Further reading
Parallel hardware accelerates verification
Incisive acceleration powered by Palladium has enabled Matsushita Electric Industrial Co to save critical design time and significantly enhance design quality for its complex, nanometre-scale designs.
SensorDynamics standardises design methodologies
SensorDynamics has selected the VCAD service model and technologies from the Encounter and Incisive platforms to enable and speed the development of highly complex microsensor applications.
Assertion checkers speed effective verification
Cadence and 0-In Design Automation have combined efforts to provide superior verification solutions to the market.
It targets the exponentially increasing complexity of the entire process spanning block, chip, and system-level verification.
Incisive Enterprise family also enables an optimal mix of e, SystemC and SystemVerilog, and includes an extensive verification IP (VIP) portfolio with a path to a high-performance system-level emulation solution with the Palladium II emulation system.
Secondly, the Incisive Design Team family is tailored for RTL design teams who are looking for low risk, powerful SystemVerilog (or VHDL and PSL) based verification solutions from assertion and test plan to RTL closure.
The family combines proven VPA methodologies, technologies, and management solutions with the market-leading Incisive Unified Simulator, Formal Verifier and Xtreme Server.
The Incisive Design Team family addresses many of the obstacles that have until now limited SystemVerilog adoption, including language maturity, VIP interoperability, proven methodologies, and the availability of supporting tools from assertion and test planning through formal analysis, simulation, acceleration and RTL closure.
Thirdly, the Incisive HDL family is based on a high-performance single-kernel simulation architecture that offers support for Verilog, VHDL and design features of the emerging SystemVerilog language.
The family also includes a desktop acceleration solution from the Incisive Xtreme series.
"Cadence continues to bring new solutions to the table that address the exploding complexities associated with our SoC development", said Ari Cohen, Vice President of Engineering, Silverback Systems.
"We are excited about how Cadence brings together software- and hardware-based solutions with verification management to bridge block, chip and system levels".
Moshe Gavrielov, Executive Vice President and General Manager of the Cadence Verification Division, said: "As design and verification methodologies have become more complicated with the advent of SoCs and nanometre geometries, the leading-edge electronics companies have had an enormous challenge adopting a large number of verification languages, methodologies and technologies to address their unique problems".
"Our customers require solutions that are integrated, tailored to their unique project team needs, and coupled with management tools and methodologies that take them from their definition of plan to closure".
"Incisive Enterprise infuses metrics throughout a verification process that is clearly becoming more and more unpredictable", said Dani Ginesi, ASIC/FPGA Development Director, Flexlight Networks "Cadence brings a productised methodology that is extremely comprehensive given the expanding scope of our verification activities, well beyond RTL, and supporting the full mix of languages that my engineers require".
Incisive is the second Cadence platform to adopt a segmented approach to delivering customer-targeted solutions.
Last month Cadence introduced a tiered range of Encounter digital IC design products scaled to different design complexities.
Encounter L products are tailored to address flat designs at 150nm and above with gate counts below 5 million gates, and Encounter XL products address large-scale, high-performance, hierarchical designs over 5 million gates at 130, 90, and 65nm.
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