Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Incisive Design Team
Edited by the Electronicstalk Editorial
Team on 26 October 2005
Teams turn to SystemVerilog-based
verification
The Incisive Design Team family is tailored for RTL design teams looking for a low-risk, yet powerful way to adopt SystemVerilog-based verification from plan to closure.
Available now from Cadence Design Systems, the Incisive Design Team family is tailored for RTL design teams looking for a low-risk, yet powerful way to adopt SystemVerilog-based verification from plan to closure The product family leverages proven verification process automation (VPA) methodologies, technologies, and management solutions from Cadence's acquisition of Verisity
This article was originally published on Electronicstalk on 24 Oct 2006 at 8.00am (UK)
Related stories
Emulator accelerates router ASIC proving
Redback Networks has selected the Cadence Incisive Design Team Xtreme III acceleration and emulation solution.
Design flow speeds multi-million-gate design
Advanced Hardware Architectures has designed and taped-out a 10-million-gate forward error correction IC using the 64bit Cadence SP and R design flow.
The Incisive Design Team family overcomes many of the obstacles that have until now limited SystemVerilog adoption.
These include language maturity, verification IP interoperability, proven methodologies, and availability of supporting tools from assertion and test planning through formal analysis, simulation, acceleration and RTL closure.
Part of a new three-tiered Incisive platform, the Incisive Design Team family includes broad SystemVerilog language support, new product integrations, and tightly coupled methodologies optimised for design teams tasked with RTL verification.
Further reading
STMicroelectronics uses Cadence VCC methodology
STMicroelectronics has selected the Cadence Virtual Component Co-Design (VCC) for both its automotive and digital consumer platform system-level design methodology and design flow.
Parasitic extraction technology joins design flow
Cadence Design Systems and Simplex Solutions have signed a technology-licensing agreement that gives Cadence exclusive distribution rights to Simplex Fire and Ice QX.
Big changes to PCB design environment
The latest release of Cadence's PCB design environment features advances planned to increase productivity and optimise the quality and performance of electronic products.
The Incisive Design Team Manager is a new version of the Incisive Verification Manager for SystemVerilog and VHDL-based verification management, from assertion test planning and tracking, to failure and RTL coverage analysis.
The Incisive Design Team Simulator has been enhanced with new SystemVerilog testbench extensions, comprehensive SystemVerilog assertion (SVA) support, and integration with the Incisive Design Team Manager.
The Incisive Design Team Xtreme Server is billed as the easiest to adopt, simulator-like acceleration and emulation solution, with SystemVerilog DPI and SVA support in Q1 2006, and integrated with the Incisive Design Team Manager.
The Incisive Design Team Formal Verifier is optimised for design team use prior to testbench availability, with new SystemVerilog SVA extensions.
All these are backed up by a packaged plan-to-closure methodology, tailored for RTL design teams adopting SystemVerilog for verification.
The methodology offers incremental steps to improve productivity, quality and predictability with maximum impact and minimum risk.
It also includes modules for dynamic and formal assertion-based verification (ABV), verification IP reuse, testbench automation, coverage, and verification management.
Plan-to-closure leverages proven eRM and sVM methodologies from the Incisive Enterprise family.
"We're very glad to see Cadence going well beyond mere language support with a solution that couples leading simulation and testbench automation solutions", said Peter Hutton, Vice President of Engineering at ARC International.
"The Incisive Design Team family delivers the technology we need with proven process automation methodology, based around the SystemVerilog language".
This new family of Design Team solutions represents the first major step in Cadence's roadmap to offer world-class verification solutions based on SystemVerilog.
As part of its "VPA Enablement" programme for SystemVerilog, Cadence engineers will continue to work closely with customers on more advanced SystemVerilog capabilities.
The programme's goal is to infuse best-in-class technology and methodology from established products such as Specman Elite and Incisive Verification Manager into SystemVerilog-based solutions.
"The SystemVerilog language has evolved faster than the tools and methodologies required to support it", said Moshe Gavrielov, Executive Vice President and General Manager of the Cadence Verification Division.
"The Incisive Design Team family represents a major step forward by leveraging Cadence's extensive verification technology, management tools and plan-to-closure methodology".
"The combined offering will allow Cadence to jump ahead with the highest-value SystemVerilog-based offering in the industry".
"Nethra is focused on meeting aggressive design schedules", said Clement Ip, Vice President of ASIC Engineering at Nethra Imaging.
"The more time we invest on design and verification up front, the faster we get to market through minimised design risk".
"Using the Incisive Design Team family from Cadence allows us to verify the design much earlier in the cycle, allowing us to hit our goals with a high level of confidence".
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
