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Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 29 November 2005
Cadence forms initiative with STARC
Cadence Design Systems has announced a cooperative quality modelling initiative with the Semiconductor Technology Academic Research Centre (STARC).
Cadence Design Systems has announced a cooperative quality modelling initiative with the Semiconductor Technology Academic Research Centre (STARC) The two companies are working together to estimate the semiconductor device outgoing quality level as a function of delay test robustness applied in manufacturing
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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The first result of the initiative is STARC's quality model's validation of Cadence Encounter True-Time Delay Test.
Delay defects slow signal transitions in nanometre-scale designs, making delay testing critically important.
Without the use of a truly effective delay test, delay defects go undetected and possibly cause failures later in the supply chain, causing significant issues in customer satisfaction and higher warranty costs.
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Assessing the effectiveness of delay testing by examination of test coverage percentage can be misleading because the actual timing of the test for each fault determines if a delay defect of a given size is detected or not.
To address this, Cadence supplies the market with Encounter True-Time Delay Test, the industry's first automatic test pattern generator (ATPG) that can automatically generate timing accurate delay tests.
"Studies of our member companies have shown that traditional delay test tools do not detect an increasing number of critical small delay defects", said Yasuo Sato, Senior Manager, Test Methodology Group at STARC.
"STARC has developed a statistical delay quality model (SDQM) methodology to quantify the effectiveness of a given delay test method".
"Cadence has successfully implemented support and validated results for this technology".
"Based on the results observed with our experiments, we expect that Encounter True-Time Delay Test can be very effective in detecting small delay defects, and thus improve the chip's outgoing quality level".
In order to better quantify the differentiated value of Encounter True-Time Delay Test, Cadence and STARC worked together to validate an SDQM that reflects fabrication process quality, design delay margin, and test timing accuracy.
The model provides an educated estimate of the quality level of the chip as a function of defects that cause delay-related failures and as a function of the timing of the test for each fault".
"Our cooperation with STARC demonstrates the advantages True-Time Delay Test provides customers", said Sanjiv Taneja, General Manager of Encounter Test, at Cadence".
"Be it in terms of detecting test escapes that later fail at system test or estimating outgoing quality levels, we are confident that True-Time Delay Test will bring significant and differentiated benefit for nanometre designs".
Part of the Cadence Encounter digital IC design platform, Encounter True-Time Delay Test is also fully compatible with Encounter Diagnostics, the industry's leading-edge yield diagnostics product.
In the effort to accelerate yield ramp, customers will benefit from the additional test efficiency of True-Time Delay Test and the subtle defects detected by it can be driven to root cause by Encounter Diagnostics.
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