Verification moves to the enterprise level

A Cadence Design Systems product story

Edited by the Electronicstalk editorial team Nov 18, 2005

The Incisive Enterprise family of products offers enterprise-level verification process automation that supports e, SystemC and SystemVerilog.

New from Cadence Design Systems, the Incisive Enterprise family of products offers enterprise-level verification process automation (VPA) that supports e, SystemC and SystemVerilog.

The new portfolio - the top tier in the segmented Cadence Incisive functional verification platform - reduces the growing predictability, productivity, and quality risks associated with complex SoC and systems development.

In addition to the Incisive Enterprise family, which is tailored for multispecialist SoC and system-development teams, Cadence offers the Incisive Design Team family, with verification solutions tailored for RTL development teams, and the Incisive HDL family, for HDL creation and simulation.

The Incisive Enterprise family is part of a new set of Cadence offerings that integrates advanced "VPA-enabled" technologies and methodologies from the Verisity acquisition with system modelling, HDL and assertion languages, high-performance formal and dynamic engines, verification IP and analysis tailored for each specialist.

Incisive Enterprise targets the exponentially increasing complexity of the verification process associated with the integration of multiple specialists spanning block, chip and system-level verification of SoCs and hardware-software systems.

"Cadence's Incisive Enterprise addresses the entire verification process from initial plan to verification closure", said Oliver Bell, Director of System-on-Chip Verification at Micronas.

"Our design and verification specialists require full solutions that support an optimal mix of languages such as e, SystemC, and SystemVerilog with a path towards system-level emulation".

The Incisive Enterprise family provides new tools, technology and methodology to automate the verification process and includes: Incisive Specman Simulator, a new product that includes a high-performance, direct kernel integration of the Incisive Simulator with block to system-level testbench automation from Specman Elite; mixed SystemC and e transaction-based verification solution linking systems and verification specialists; Enterprise Manager, enhanced for enterprise use with integration to all Incisive engines, languages, and coverage tools; Incisive Palladium hardware-assisted verification for specialists doing high-speed acceleration, HW/SW coverification, system-level and post-silicon verification; Incisive Enterprise plan-to-closure productised methodology, combining widely adopted and mature reuse with proven transaction-level modelling and system-level verification methodologies; and encapsulation of Incisive Design Team family of products and methodologies, including formal analysis and SystemVerilog support.

"As design and verification methodologies have become more complicated with the advent of SoCs and nanometre geometries, the leading-edge electronics companies have been forced to create teams of specialists".

"Each specialist requires a best-in-class solution tied together into an overall plan-to-closure methodology", said Moshe Gavrielov, Executive Vice President and General Manager of the Cadence Verification Division.

"Our customers require a process that is highly automated and managed with metrics for maximum visibility, predictability, resource utilisation, productivity and system-level quality".