Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter RTL Compiler GXL
Edited by the Electronicstalk Editorial
Team on 06 December 2005
Synthesis package promises optimal QoS
Encounter RTL Compiler GXL is an upgraded version of the Cadence Encounter RTL Compiler global synthesis technology, and the top-tier of the segmented Cadence synthesis product line.
Encounter RTL Compiler GXL is an upgraded version of the Cadence Encounter RTL Compiler global synthesis technology, and the top-tier of the recently announced segmented Cadence synthesis product line This product helps leading-edge designers deliver smaller, faster and cooler chips in less time
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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New capabilities include advanced low-power synthesis with top-down multiple-supply-voltage (MSV) optimisation, automatic physical layout estimation (PLE), top-down retiming for high-performance designs, multiple-CPU superthreading to improve customer productivity, and single-pass multimode synthesis.
Advanced low-power-design techniques create new challenges for traditional synthesis tools.
Encounter RTL Compiler global synthesis is architected to concurrently optimise timing, area and power, thus resulting in optimal quality of silicon (QoS), even under challenging low-power requirement.
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New top-down MSV optimisation lets low-power designers use synthesis more easily and efficiently to design optimal voltage levels across multiple logic domains in order to determine the best solution for lowering power while meeting timing requirements.
Since synthesis is aware of the voltage domains, it creates a better design for physical implementation, enabling a smooth flow.
"Voltage scaling is a great technique for reducing overall static and dynamic power consumption, but its implementation presents many challenges", said Alessandro Uguzzoni, R and D Manager at Accent.
"Encounter RTL Compiler top-down MSV synthesis enables us to experiment early on with different voltage domain scenarios to find the best partitioning tradeoff".
"Its MSV-aware optimisation helps greatly in achieving timing convergence during the physical implementation phase".
In order to effectively consider submicron physical effects during the early synthesis process, a new breakthrough modelling technique improves the overall QoS with better timing, area, and power.
The new PLE uses innovative, proprietary methods to adaptively model physical effects before logic gates exist.
This new modelling has no impact on runtime and eliminates the need for traditional wireload models.
"The problems with wireload models in today's process geometries are well-known", said Karl Pfalzer, Staff Engineer at ATI Technologies Silicon Valley.
"But that has been the only way to effectively model interconnect delay during synthesis from RTL to gates, when the logic structure is being created".
"We have tried experiments on some blocks from our designs and have found that using PLE in Encounter RTL Compiler provides the best correlation with and best results out of place and route".
Retiming is a powerful optimisation technique that has traditionally been used only in special high-performance designs because of difficult methodology requirements.
This new capability makes retiming easy for a wide range of designs, enabling improvements in a design's frequency or area.
This capability also works seamlessly with formal verification tools.
"Our V10LAN transceiver uses large digital filters that we needed to pipeline", said Ed Beers, Principal Design Engineer at Vativ Technologies.
"We integrated retiming into our top-down synthesis with Encounter RTL Compiler and we were able to reduce our pipeline register count by 45% versus our previous flow".
"Retiming in Encounter RTL Compiler enabled us to implement our design at 130nm while meeting our timing and area goals".
"I was amazed to discover how much other tools were leaving on the table".
"I had thought that synthesis was pretty mature".
The superthreading capability speeds synthesis runtimes by up to three times with no impact on QoS, thus improving productivity and time to market.
It makes efficient use of multiple processors or workstations transparent to the user, and guarantees identical high QoS results as a single processor run.
"Our chips are roughly 2 million instances in size", said Subramanian Krishnamoorthy, Director of the Design Solutions Group at Toshiba America Electronic Components.
"We are using Encounter RTL Compiler for preconditioning the gate-level netlist before implementing the design using TAEC's Pinnacle flow based on SoC Encounter".
"Fast turnaround time of this preconditioning process is critical to the overall implementation productivity".
"Encounter RTL Compiler's superthreading enabled us to speed this process twofold".
"It produces identical netlist and timing performance as the preconditioning process without the superthreading feature".
Modern chip design often requires multiple functional modes of operation and multiple power modes in addition to multiple test modes.
Traditional methodologies require either manual merging of the constraints for different modes, or multiple iterative runs which may not achieve closure on all goals.
Encounter RTL Compiler multimode synthesis enables single-pass optimisation and analysis using constraints for all modes simultaneously.
"We continue to rapidly advance our global synthesis technology to raise the bar for the industry", said Dr Chi-Ping Hsu, Corporate Vice President at Cadence.
"This release further extends Encounter RTL Compiler's ability to deliver the fastest path to the highest QoS".
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