Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter GXL
Edited by the Electronicstalk Editorial
Team on 25 January 2006
65nm design flow maximises platform
benefits
Fujitsu has adopted the Cadence Encounter digital IC design platform in its new internal reference design flow targeted at 65nm chips.
Fujitsu has adopted the Cadence Encounter digital IC design platform, with Encounter RTL Compiler GXL and SoC Encounter GXL technology, in its new internal reference design flow targeted at 65nm chips The Encounter-based flow has, to date, produced 150 high-end production ASICs at or below 130nm with all first silicon success, out of which about 30 designs were developed at 90nm
This article was originally published on Electronicstalk on 6 Dec 2005 at 8.00am (UK)
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"At 65nm there are new design challenges such as yield, process variation and leakage power", said Satoshi Andou, General Manager, Design Platform Development Division, Electronic Devices Business Unit of Fujitsu.
"We evaluated the Cadence Encounter GXL technologies over the past six months and have been intensively incorporating its new global synthesis and physical implementation technologies into our new reference design flow for 65nm".
"We appreciate the Cadence team's dedicated contribution to Fujitsu's successful launch of our 65-nanometre technology".
To address design-for-yield (DFY) concerns at 65nm, Fujitsu and Cadence worked together to adopt the Cadence SoC Encounter GXL system's yield-aware physical implementation features.
As a result of this joint collaboration, the 65nm reference flow will also include SoC Encounter's Masterplan automatic floorplanner, global physical synthesis (GPS), Encounter NanoRoute Ultra routing, verification and chip-finishing technology.
CeltIC Nanometre Delay Calculator (NDC) and VoltageStorm static analysis are also available to provide signoff-quality SI- and IR-aware timing.
Encounter RTL Compiler logic synthesis is also included in the reference design flow, and Fujitsu has started to evaluate new advanced synthesis features, including automatic physical-layout estimation (PLE) to address 65nm design challenges.
Finally, Encounter's RTL-to-GDSII low-power flow enables seamless multi-supply-voltage and multi-threshhold-voltage (Vt) designs, which is featured in the Fujitsu's leading-edge low-power solution using its low-power library.
"As a Premier Design Partner of Fujitsu, we are pleased that our advancements in synthesis, signal-integrity-based timing closure and low-power-design solutions have contributed to Fujitsu's success in a wide variety of markets, including IP and ASIC", said Wei-Jin Dai, Corporate Vice President, R and D for Cadence.
"We applaud Fujitsu's success in maximising the benefits of the Cadence Encounter platform".
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