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Design and Development Software
News Release from: Cadence Design Systems | Subject: 90nm reference flow
Edited by the Electronicstalk Editorial
Team on 28 February 2006
Reference flow optimises 90nm SoC
designs
A 90nm reference flow addresses power-management and design-yield issues.
Cadence Design Systems has developed a 90nm reference flow that addresses power-management and design-yield issues The new flow is part of an ongoing collaboration with IBM and Chartered Semiconductor Manufacturing
This article was originally published on Electronicstalk on 26 May 2004 at 8.00am (UK)
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The companies developed this design reference flow for the 90nm low-power process technology on the IBM-Chartered Common Platform and to provide innovative solutions to accelerate time to market for system-on-chip (SoC) designs.
The new RTL-to-GDSII reference flow is based on the Cadence Encounter digital IC design platform and enables higher productivity and improved quality of silicon (QoS).
The reference flow addresses critical low-power design challenges, from chip prototyping through power, timing and area optimisation.
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The Cadence SoC Encounter GXL RTL-to-GDSII system enables timing-aware leakage power and dynamic power optimisation, using power techniques such as multiple supply voltages, multiple-Vt optimisation, and clock gating.
This optimisation helps designers improve timing closure and reduce device area, while lowering power consumption without compromising performance.
"IBM and Chartered continue to drive the Common Platform for 90nm designs and beyond", said Steve Longoria, vice president of Semiconductor Common Platform for IBM Systems and Technology Group.
"We worked closely with Cadence to enable a low-power, yield-aware design methodology to reduce design and manufacturing risk".
"This next phase in the design chain collaboration with Cadence expands our open ecosystem based on collaborative innovation".
The flow addresses nanometre defect yield issues with yield analysis and optimisation capabilities embedded in critical implementation stages such as physical synthesis and routing.
For yield analysis, full-chip or block-level defect yield losses are assessed based on factors such as critical area and cell yields.
An innovative yield prototyping capability enables designers to choose full-chip floorplanning strategies with visibility of yield considerations before committing to a physical architecture for the chip, allowing them informed design choices to speed yield ramp.
For nanometre designs, wiring has growing impact on final chip yield.
This is addressed by optimising double-via insertion, wire spacing and other factors concurrently during routing, instead of a separate post-processing step.
"Our collaboration with the leaders in the Common Platform - IBM and Chartered - aligns industry breadth and depth to address the complexity of design facing our customers today", said Jan Willis, Senior Vice President, Industry Alliances, at Cadence.
"This 90nm low-power and yield-aware reference flow is the next step in our ongoing design chain collaboration to enable customers to ramp high-quality products to volume through the Common Platform".
The flow incorporates several innovative Cadence technologies, including Encounter RTL Compiler global synthesis, the SoC Encounter GXL system, Encounter Test, Encounter Conformal Low-Power verification, and Cadence QRC extraction.
Other Cadence components include VoltageStorm Dynamic Gate power rail analysis, and CeltIC Nanometre Delay Calculator (NDC), using the highly accurate effective current source delay model (ECSM) to enable designers to reduce time-to-volume for low-power consumer applications.
ARM Metro low-power products, part of its family of Artisan physical IP, are used for the flow development.
"Support from our EDA partners like Cadence allows us to provide our customers with solutions that accelerate their path to silicon while offering them the flexibility benefits and sourcing options of our collaborative strategy with IBM", said Kevin Meyer, Vice President of Worldwide Marketing and Platform Alliances at Chartered.
"We are pleased to continue working together with Cadence in providing advanced low-power technologies for 90nm design that further enhance the Common Platform".
Cadence, Chartered, IBM and Samsung are working on a reference flow targeted at the Common Platform's 65nm LP process.
This 90nm low-power, yield-aware design reference flow is available immediately.
This reference flow kit contains a reference design, documentation and scripts to run the reference flow.
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