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Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 28 February 2006
Power-management methodology is enhanced
The Silicon Design Chain Initiative has published announced a second, enhanced version of its power-management methodology.
Industry leaders, working through the Silicon Design Chain Initiative (SDC), have announced a second, enhanced version of its power-management methodology and implementation up to tapeout of the ARM 1136JF-S processor as proof of the methodology and its interdependent technologies The new methodology is based on ARM IP, the Cadence Encounter digital IC design platform, and TSMC's Reference Flow 6.0
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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The new methodology expands on the techniques announced by the initiative last year by adding enhanced automated methods for dynamic and leakage-power reduction including power-shutdown techniques, low-power design-for-test (DFT) and low-power formal verification working in concert with the ARM Advantage physical IP, including its Power-Management Kit, for the TSMC 90nm G process.
These methods are designed to enable designers to balance power and performance in designing systems-on-chips (SoCs).
By validating these methods in a widely used ARM processor design, the initiative makes it easier for designers to adopt these techniques in their low-power design projects.
"It is no longer sufficient for collaboration to be one-on-one-it takes a design chain", said Jan Willis, Senior Vice President of Industry Alliances at Cadence.
"Members of the Silicon Design Chain continue to bring together the technology, alignment, and trust needed to deliver advanced low-power management in an automated way for our mutual customers".
The second version of the Initiative's power-management design methodology features new power domain-aware capabilities that include power gating for leakage reduction, low-power DFT, low-power formal verification, and top-down multiple-voltage synthesis.
Cadence Encounter RTL Compiler synthesis and implementation flow eases designers' use of power-gating techniques and automates manual optimisation processes to help designers turn around low-power designs much faster.
Low-power DFT and ATPG capabilities, within Cadence Encounter Test, help limit power consumption during test application while ensuring comprehensive test coverage across timing fault-sensitive, low-voltage circuitry.
Power-saving capabilities minimise overall switching during testing, and support low-power designs by detecting small delay defects often missed in other test schemes.
As designers adopt new tools and methodologies to address the challenges of low-power design, it is critical that they can verify that low-power circuitry has been implemented correctly.
Building on the Initiative's first version of its power management methodology, Cadence Encounter Conformal Low Power provides a combination of transistor abstraction, equivalency checking, and functional verification technology to verify low-power designs.
Transistor and logical analysis capabilities help address issues with leakage.
The solution can validate that designers have correctly instantiated isolation cells such as those in the ARM Power Management Kit and that they are in the proper states to control the isolation function.
In addition, equivalence-checking capabilities ensure that advanced power-gating techniques do not introduce functional bugs through the implementation flow.
"Power consumption continues to be the most challenging issue for the digital-entertainment and mobile-communications markets", said Neal Carney, Vice President of Marketing, Physical IP, ARM.
"The solution to this challenge resides with broad cross industry collaboration".
"The Silicon Design Chain with ARM, TSMC, Cadence and Applied Materials is one of the leading examples of this with collective delivery of a 'proof of concept' that validates methodologies in actual designs".
The Silicon Design Chain's newly expanded power-management methodology is now available through the Initiative's member companies.
A white paper about this methodology can be found at www.silicondesignchain.org.
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