Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter RTL Compiler
Edited by the Electronicstalk Editorial
Team on 28 March 2006
Speedy synthesis shrinks ASICs and cuts
time
Hitachi Communication Technologies has improved synthesis turnaround time by 50 to 70% with Cadence Encounter RTL Compiler global synthesis.
Hitachi Communication Technologies has improved synthesis turnaround time by 50 to 70% with Cadence Encounter RTL Compiler global synthesis Encounter RTL Compiler, a key technology of the Encounter digital IC design platform, helped Hitachi Communication Technologies to achieve faster time to market on six 130nm ASIC designs
This article was originally published on Electronicstalk on 19 Feb 2004 at 8.00am (UK)
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Hitachi Communication Technologies is a leader in the design, development and worldwide sales of information and communication system-related products, featuring optical access, broadband mobile and IP networks.
The six ASICs that the company taped out with Encounter RTL Compiler synthesis were a combination of wireline and wireless communications chips.
A long-time user of Cadence technology, Hitachi Communication Technologies initially adopted Encounter RTL Compiler synthesis because of its ability to reduce chip area.
This latest achievement stands to expand the company's commitment to Cadence Encounter synthesis even further.
"We adopted Encounter RTL Compiler synthesis because it helped us to reduce area by an average of 25%".
"The faster synthesis turnaround time that Encounter RTL Compiler delivered enabled us to spend more time focusing on verifying last-minute modifications of the design specification", said Hideya Sato, CAD Department Manager in the Carrier Network Systems Division at Hitachi Communication Technologies.
"Cadence Encounter RTL Compiler synthesis has proven to be a complete synthesis solution that delivers us benefits over our existing solution, and we are considering adopting it as the standard synthesis tool throughout the company".
Encounter RTL Compiler global synthesis has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route.
Cadence defines the combination of these metrics as quality of silicon (QoS).
Encounter RTL Compiler is available in L, XL and GXL configurations in conjunction with Cadence's segmentation strategy.
"We are excited that our global synthesis technology helped improve time to quality for Hitachi Communication Technologies on these six tapeouts", said Dr Chi-Ping Hsu, Corporate Vice President at Cadence.
"Encounter RTL Compiler synthesis is a production-proven tool that delivers real business benefits".
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