Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: SMIC AMS reference flow
Edited by the Electronicstalk Editorial
Team on 17 April 2006
Reference flow speeds mixed-signal
design
An analogue mixed-signal reference flow addresses the needs of designers developing ICs for the consumer, networking and wireless markets.
Cadence Design Systems and Semiconductor Manufacturing International Corporation (SMIC) have jointly developed an analogue mixed-signal (AMS) reference flow to address the needs of designers developing ICs for the consumer, networking and wireless markets The block-level reference flow is based on SMIC's 0.18um multimode, radio-frequency process design kit (PDK) and the Cadence Virtuoso custom design platform and Design for Manufacturing (DFM) technologies
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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"As a leader in analogue mixed-signal design solutions, Cadence has provided its unique technology and expertise to create this reference flow".
"This solution will help to facilitate analogue mixed-signal design for the growing consumer, networking and wireless markets".
"Cadence and SMIC aim to continue collaborating on improving designers' productivity by focusing on mainstream and advanced process technologies", said Mike McAweeney, Vice President of Business Development of Industry Alliances at Cadence.
"Cadence has a strong worldwide foundry access team that works with leading foundries to develop PDKs and reference flows that enable customers to speed up product development cycles and reduce design failure risks".
"The AMS reference flow is a result of the continuing efforts of Cadence and SMIC to ensure customer success through collaboration".
The SMIC-Cadence analogue mixed-signal reference flow, based on OpenAccess 2.2, the industry open database standard, provides designers an optimised and predictable schematic-to-GDSII flow.
The flow provides a starting point for design teams creating SoCs or putting together a flow of their own.
The flow incorporates several Cadence technologies, including Virtuoso Spectre circuit simulator, Virtuoso UltraSim full-chip simulator, Virtuoso Schematic Editor, Virtuoso analogue Design Environment, Virtuoso Specification-driven Environment, Virtuoso Chip Assembly Router, Virtuoso XL Layout Editor, Assura DRC/LVS Verifier and Cadence QRC Extraction.
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