Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Support for TSMC 65nm process
Edited by the Electronicstalk Editorial
Team on 19 May 2006
Software supports 65nm process
introduction
Cadence device and interconnect models, design flows and design for manufacturing technologies support Taiwan Semiconductor Manufacturing Company's 65nm technology.
Cadence device and interconnect models, design flows and design for manufacturing (DFM) technologies support Taiwan Semiconductor Manufacturing Company's (TSMC) 65nm technology By providing designers an integrated methodology to address 65 nanometres, Cadence can help shorten the design cycle, maximise first-pass silicon success, and address manufacturing issues throughout the design chain
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
Related stories
Design flow speeds multi-million-gate design
Advanced Hardware Architectures has designed and taped-out a 10-million-gate forward error correction IC using the 64bit Cadence SP and R design flow.
STMicroelectronics uses Cadence VCC methodology
STMicroelectronics has selected the Cadence Virtual Component Co-Design (VCC) for both its automotive and digital consumer platform system-level design methodology and design flow.
"Lowering barriers for advanced design is critical to increasing the adoption rate for 65-nanometre technology", said Edward Wan, Senior Director of Design Services marketing at TSMC.
"We work with Cadence to achieve a faster ramp to volume by allowing designers to address manufacturing and lithography effects".
Technology files for Cadence QRC Extraction, as well as device models for the Cadence Virtuoso Spectre Circuit Simulator, are now available from TSMC.
Further reading
Parasitic extraction technology joins design flow
Cadence Design Systems and Simplex Solutions have signed a technology-licensing agreement that gives Cadence exclusive distribution rights to Simplex Fire and Ice QX.
Big changes to PCB design environment
The latest release of Cadence's PCB design environment features advances planned to increase productivity and optimise the quality and performance of electronic products.
Windows-based suite speeds PCB design
The Orcad Unison Suite from Cadence is a full front-to-back Windows-based flow that offers PCB designers improved productivity and reduced time to market through tool integration and task automation.
These technology files and device models have been validated for TSMC's 65-nanometre Nexsys process design rules.
Designers using Virtuoso UltraSim Full-chip Simulator and Virtuoso AMS Designer Simulator can use the same device models as Virtuoso Spectre Circuit Simulator via the Common Model Interface.
Cadence QRC Extraction accounts for process variation effects to ensure design manufacturability.
Cadence simulation technology has also been updated with the latest BSIM device models incorporating key 65-nanometre effects on device characteristics, such as LOD/STI and well proximity, to enhance silicon-accurate results for designs using TSMC's 65-nanometre Nexsys(SM) process.
65-nanometre designs face complex issues, such as an exponential increase in leakage power, tight manufacturing parameters, and new extraction requirements.
Cadence and TSMC are continuing their design-chain collaboration to address these issues through comprehensive design kits and reference flows for TSMC's 65-nanometre process.
These design kits and flows help provide a smooth path from design through physical implementation for customers using the Cadence Encounter digital IC design, Virtuoso custom design, and Allegro system interconnect design platforms.
Cadence DFM technologies that are tied to TSMC's 65-nanometre process include critical area analysis (CAA), lithography process checking (LPC), and the physics-based modelling of chemical mechanical polishing (CMP) effects required for analysis of full-chip thickness variation.
TSMC process-specific manufacturing data is incorporated into these technologies to improve design capabilities and productivity for designers working on complex 65-nanometre SoCs.
The Cadence DFM approach addresses nanometre defect yield issues with the Cadence SoC Encounter GXL RTL-to-GDSII system, which provides CAA and optimisation within the Encounter platform.
This enables yield optimisation to be considered concurrently with power, timing, signal integrity and area at any point in the design flow - from prototyping and physical synthesis to manufacturing-aware extraction and chip finishing.
For LPC, Cadence provides resolution enhancement techniques (RET) capabilities within the design environment to identify locations in the design where common lithography process variations may cause severe printability issues that would affect yield.
In addition, Cadence technology for CMP modelling of full-chip thickness variation accurately predicts systematic variation in interconnect layer thickness that results from planarisation operations (ie CMP).
The resulting predictions can be used to identify thickness-related yield hot spots or to shrink overly conservative thickness guardbands.
"Cadence continues to take a leadership role in accelerating time to volume for 65-nanometre designs", said James Miller Jr, Executive Vice President, Products and Technologies Organisation, at Cadence.
"At advanced process nodes, designers face increasing impact from physical and lithographic effects that significantly degrade circuit performance and yield".
"By providing solutions that more accurately model 65-nanometre manufacturing effects, we can help designers anticipate manufacturing and lithography-based concerns during the design process, enabling more manufacturable, high-yielding products to be brought to market sooner".
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
