Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter True-Time Test
Edited by the Electronicstalk Editorial
Team on 23 June 2006
Timing-aware test generation cuts design
delays
Comit Systems has standardised its automatic test pattern generation (ATPG) flow on Cadence Encounter Test.
Comit Systems has standardised its automatic test pattern generation (ATPG) flow on Cadence Encounter Test This expands Comit's commitment to Cadence's powerful, synergistic front-end technologies and follows its successful standardisation on Cadence Encounter RTL Compiler global synthesis last year
This article was originally published on Electronicstalk on 27 Oct 2006 at 8.00am (UK)
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After previous experience with other DFT and test generation technologies, Comit Systems chose Encounter True-Time Test to maximise test coverage and first-pass manufacturing test success for its growing customer base.
After a smooth, simple migration process, Encounter True-Time Test helped Comit's design service customers meet stringent quality and time to market requirements with a set of compact, high-coverage, high-quality manufacturing tests.
Its timing-aware test generation capability enabled Comit customers to detect small delay defects commonly missed by traditional ATPG approaches.
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"We looked at the marketplace and found that Cadence's integrated offering of Encounter Test and Encounter RTL Compiler synthesis is a powerful combination unmatched in the industry", said Venkat Iyer, vice president of Engineering at Comit.
"As a leading-edge design house, we must be able to quickly and efficiently adopt the best possible technology".
"We were able to migrate to Encounter Test in a short time with minimal support".
"Encounter True-Time Test's proven track record and integration with Encounter RTL Compiler synthesis will continue to help us deliver our customers superior quality ATE test patterns in the shortest time possible".
Comit Systems provides engineering services for electronic product development through chips, board, software and system design.
The combination of Encounter RTL Compiler and Encounter True-Time Test gave the company confidence that it would continue to meet its design goals of timing, power, area, and testability for first time right, high quality test coverage vectors.
Exploding design complexity and nanometre-scale silicon geometries make test critical to the success of modern system on chips (SoCs).
Major challenges include creating effective full-chip test architectures, minimising cost of test and tester time, and maximising test coverage and product quality.
Encounter Test delivers advanced test solutions from RTL to silicon.
Encounter True-Time Test uses actual design timing to generate at-speed and faster-than-at-speed tests that deliver unparalleled product quality.
Encounter RTL Compiler synthesis with DFT insertion has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route.
"Comit's adoption of Encounter Test technology is an endorsement of the differentiated value the Encounter platform's integrated synthesis, DFT and test generation technologies delivers", said Sanjiv Taneja, Vice President of R and D at Cadence.
"As an important partner, we are very honoured by Comit's expansion from Encounter RTL Compiler global synthesis to Encounter Test".
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