Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Cadence Precision Router
Edited by the Electronicstalk Editorial
Team on 29 June 2006
Next-generation IC router thinks outside
the grid
The Cadence Precision Router is a space-based, full-chip and block routing solution for advanced mixed-signal, analogue and custom digital designs.
The Cadence Precision Router is a space-based, full-chip and block routing solution for advanced mixed-signal, analogue and custom digital designs The product speeds design and manufacturing convergence by allowing designers to model manufacturing effects during the design process for design performance closure and faster time to volume manufacturing ramp-up
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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Complex interconnect rules, including those at 65 and 45nm, challenge the physical modelling capability of traditional shape-based and gridded routers.
Cadence Precision Router uses a three-dimensional, space-based modelling approach to analyse true shapes and intervening physical spaces to handle the complexity inherent in ever-increasing design sizes and shrinking process geometries.
This model provides greater accuracy, precision and flexibility than shape-based approaches in creating, checking and manipulating interconnects, and minimises the steps to design and manufacturing convergence.
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Cadence Precision Router operates seamlessly with the Virtuoso custom design platform and provides a hierarchical and constraint-driven design closure environment with highly incremental interactive and automatic routing.
Cadence Precision Router was architected to optimise tiered and preferred manufacturing rules concurrently with electrical objectives, allowing designers to achieve higher quality results in the shortest amount of time.
Silicon-validated results for Cadence Precision Router have shown orders of magnitude improvement in performance and capacity.
The product also features multi-threaded routing for fast turnaround on the large designs that are common at leading-edge process nodes.
"Cadence Precision Router reduced our time to closure, compared with our previous design methodology", said Mark Papermaster, Vice President of Microprocessor and Systems Technology Development at IBM Corp.
"By leveraging the solution's tiered constraint system, we were able to address our sophisticated manufacturing and high-performance design constraints with excellent quality of results".
"As an early partner for Cadence's next-generation, space-based, interconnect system, we saw the value of a single platform for design-for-manufacturing (DFM) and design-for-yield (DFY) interconnect optimisation and creation".
"As a result, we have adopted both Cadence Chip Optimiser and Cadence Precision Router for our 65- and 45-nanometre microprocessor designs".
With shrinking process geometries, designers must address constantly evolving design rules, satisfy electrical performance targets, manage ever-increasing design sizes and even perform time-consuming, manual intervention after routing.
To meet these challenges, Cadence Precision Router offers a gridless, three-dimensional, space-based routing architecture.
This solution overcomes the performance and capacity limitations of shape-based routers, and the accuracy and flexibility limitations of gridded routers, allowing designers to model advanced manufacturing processes and design constraints that are used up front in the design process for maximum control and exceptional results.
Especially suitable for high-performance blocks and full-chip designs, Cadence Precision Router also features specialty mixed-signal routing, incremental in-core electrical analysis, and DFM and DFY optimisation.
"The deep level of collaboration between Cadence and IBM has produced great results in improving turnaround time and yield optimisation", said Leon Stok, Director of EDA at IBM Corp.
"Cadence Chip Optimiser and Cadence Precision Router provide an outstanding, modular platform for tight integration with our internal toolset".
"The co-operation between Cadence and IBM is an excellent example of the collaboration needed to create next-generation, electrically- and manufacturing-aware physical implementation solutions".
Cadence Precision Router, along with Cadence Chip Optimiser, is built on innovative technology developed in Cadence's Project Catena technology incubator and can be applied to a broad range of design styles and process nodes.
Using Cadence Precision Router in their design flows, leading integrated device manufacturers worldwide have produced tapeouts down 45nm in the consumer, business and computing markets.
"Process variability, increasingly complex design rules and manufacturing effects from lithography and chemical mechanical polishing (CMP) are becoming first-order effects", said Ted Vucurevich, CTO of Advanced Research and Development at Cadence.
"To tackle these issues, we've developed an entirely new architectural approach for Cadence Precision Router where physical, electrical, and logical perspectives can be presented to the designer all at once".
"This approach is the cornerstone of convergence and paves the way for designers to achieve the superior quality of results, high capacity and increased throughput needed for routing tomorrow's most advanced designs".
Cadence Precision Router is part of Cadence's growing family of design and manufacturing closure technologies that help designers address both design performance and manufacturing and yield issues throughout the design flow.
Cadence Precision Router is an OpenAccess-based application that works seamlessly with the Virtuoso custom design platform and is complementary to the Encounter digital IC design platform.
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