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News Release from: Cadence Design Systems | Subject: Functional Verification Kit for ARM technology
Edited by the Electronicstalk Editorial
Team on 28 June 2006
Kit verifies the truth about ARM designs
The Cadence Functional Verification Kit for ARM technology, presenting design teams with a low-risk path to verification closure when verifying ARM processor-based designs.
The Cadence Functional Verification Kit for ARM technology, presenting design teams with a low-risk path to verification closure when verifying ARM processor-based designs The kit covers the verification process from architectural verification to system validation for both hardware and software - all tied together with Cadence's proven Incisive Plan-to-Closure Methodology
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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"ARM and Cadence continue to deliver solutions that provide measurable value to our mutual customers", said Mike Inglis, Executive Vice President of Marketing, ARM.
"This kit collaboration, using Cadence's Plan-to-Closure Methodology and ARM-technology-certified Amba verification IP, reinforces our commitment to accelerate verification closure for producing industry-leading ARM processor-based designs".
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This Cadence Kit contains block-, chip-, and system-level flows and verification methodology tailored for ARM processor-based designs using the Cadence Incisive platform, Cadence applicability consulting, an ARM926 processor-based representative design to demonstrate the methodologies, and a full suite of ARM technology-certified Amba methodology-based verification IP (VIP).
The VIP includes reusable verification plans, Amba compliance metrics, advanced testbenches, formal and accelerated protocol assertions, accelerated transactors, cycle-callable ARM processor models, and ARM emulation LogicTiles.
"NeoMagic's MiMagic application processor family delivers powerful multimedia performance at extremely low power for handheld systems".
"As we add more performance and features to ARM processor-based SoCs, our verification challenges increase significantly", said Dr Sudhir Chandratreya, Vice President, VLSI Design and Technology, NeoMagic.
"Our team has a very successful history verifying our SoC designs with Cadence's verification automation solutions".
"This ARM and Cadence collaboration to deliver a functional verification kit to streamline the path to Amba compliance and verification closure is a very welcome and important step".
Amba methodology is an integral part of this Cadence Kit and is a widely-adopted and open specification available for internal System-on-Chip (SoC) communication.
ARM has awarded Amba 3 AXI Assured certification and Amba 2 AHB compliance to Cadence's Amba methodology-based Incisive VIP.
This certifies the VIP correctly implements the specifications and the ARM eXtensible Verification Component (XVC) simulation interface.
In addition, Cadence's AXI and AHB executable verification plans (vPlan) are certified to provide Amba compliance to customers.
"The Cadence Functional Verification Kit for ARM offers significant enhancements for the challenging task of verifying complex ARM processor-based designs", said Moshe Gavrielov, executive vice president and general manager of the Cadence Verification Division.
"Design and verification teams now have at their disposal a powerful set of technologies, supported by a proven methodology, to help them speed their designs to high-quality silicon".
The Cadence Functional Verification Kit for ARM further strengthens the Cadence Kits approach to solving the complex design challenges of electronics.
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