Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: X Architecture
Edited by the Electronicstalk Editorial
Team on 03 July 2006
Architecture cuts handset chipset down
to size
Agere has completed the design and implementation on a next-generation, 90-nanometre, mobile handset chipset using the Cadence X Architecture and successfully taped it out.
Agere has completed the design and implementation on a next-generation, 90-nanometre, mobile handset chipset using the Cadence X Architecture and successfully taped it out As a member of Agere's Vision mobile baseband family of 2.5G and 3G solutions, this chip was taped out to TSMC's 90-nanometre semiconductor process technology, making Agere the first fabless semiconductor company to tape out a 90-nanometre X Architecture production design
This article was originally published on Electronicstalk on 15 Jun 2005 at 8.00am (UK)
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Agere and Cadence's new design collaboration expands on the two companies' existing relationship based on the Cadence SoC Encounter system, and takes advantage of the significant cost and power benefits enabled by the Cadence X Architecture for Agere's advanced Vision mobile handset architecture.
"Agere is impressed with the die-size reduction and reduced power dissipation resulting from the wirelength reduction achieved with the X Architecture", said Craig Garen, Vice President of Mobility Product Development with Agere.
"Our company has confirmed that the Cadence X Architecture has realised a wirelength reduction of more than nine metres - approximately 30% - versus previously used 'Manhattan' routing in the same technology".
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"The ease with which the Cadence X Architecture integrated into our signoff flow enabled us to meet our aggressive tape-out schedule".
"TSMC is focused on enabling innovative solutions like the X Architecture for our customers", said Ed Wan, Senior Director of TSMC's Design Services Marketing.
"We're pleased to see key customers like Agere reap the benefits of our collaboration with Cadence on the X Architecture".
"Market leaders such as Agere recognise that innovative technologies such as the X Architecture are essential to maintain a competitive edge in today's marketplace", said Kalyan Thumaty, Vice President and General Manager of X Architecture at Cadence.
"Agere's adoption of the Cadence X Architecture for its next-generation mobile handset chips is a strong endorsement of our unique offering".
"With this latest 90-nanometre tapeout success, the Cadence X Architecture continues its momentum at leading fabless semiconductor companies worldwide".
The X Architecture represents a new way of orienting a chip's microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle "Manhattan" routing.
The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly less wirelength and fewer vias (the connectors between wiring layers).
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