Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Cadence Encounter Test
Edited by the Electronicstalk Editorial
Team on 14 July 2006
Diagnostics technology lead extended
Industry-award winning Cadence encounter test expands data compression and yield diagnostic offerings to address escalating manufacturing costs and yield ramp.
Cadence Design Systems has announced it is extending its technology leadership in test and yield diagnostics with new compression and yield diagnostics capabilities The new release of Cadence Encounter Test addresses the escalating cost of manufacturing high quality silicon with expanded support for non-proprietary, on-chip exclusive-or (XOR) test data compression structures
This article was originally published on Electronicstalk on 9 Mar 2005 at 8.00am (UK)
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Cadence Encounter Test Architect is billed as the industry's first full-chip test architecture development product.
Timing-aware test generation cuts design delays
Comit Systems has standardised its automatic test pattern generation (ATPG) flow on Cadence Encounter Test.
The new compression capability enables multi-vendor interoperability between Automatic Test Pattern Generation (ATPG) and diagnostics products and allows the use of a single pass diagnostic flow.
"High test coverage and solid support for multiple test data compression architectures are key requirements toward achieving our quality goals relative to cost of test and cost of product," said Raj Raina, manager, DFM/DFT Methodology, Freescale Semiconductor.
"We are very pleased with the addition of the latest XOR compression architecture in Encounter Test".
Further reading
Software spots chip flaws
The Cadence Encounter Test solution was able to help IBM meet its goals for quality and volume production.
Design flow speeds multi-million-gate design
Advanced Hardware Architectures has designed and taped-out a 10-million-gate forward error correction IC using the 64bit Cadence SP and R design flow.
"It provides minimum design impact, exceeds our compression requirements, achieves the necessary test coverage, and supports one-pass diagnostics methodology".
This new test capability supports input side decompression based on an XOR spreading network fan-out, while on the output side, the compression uses XOR tree compaction with optional x-state masking.
This augments Cadence's highly effective OPMISR+ (on-product multiple input shift register) architecture widely deployed by Cadence Encounter Test customers.
Either compression architecture is easily inserted with Test and Measurement World's 2005 Best in Test Award winning Encounter Test Architect.
In addition, the Encounter Test Diagnostics capability has been expanded from logical domain to localisation of physical structures within the design that cause yield loss.
These structures are highlighted with a new, intuitive, easy-to-use, full-function physical browser.
This browser quickly correlates a diagnostic callout to a net, including its metal layer and encompassing vias and contacts to help speed Physical Failure Analysis (PFA).
"This new release continues Encounter Test's strong tradition of innovation and integration for delivering higher value to our customers," said Sanjiv Taneja, vice president of R and D at Cadence.
"Our customers will benefit from accelerated yield ramp and lower test cost enabled through new innovations in compression and yield diagnostics embodied in this release".
Cadence Encounter Test is a key technology of the Cadence Encounter digital IC design platform and helps delivers the industry's most advanced test solution from RTL to silicon.
This new technology is available now.
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