Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter and Allegro
Edited by the Electronicstalk Editorial
Team on 20 July 2006
Design and system interconnect go with
the flow
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 7.0.
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's Reference Flow 7.0 With this reference flow, which supports designs targeting TSMC's Nexsys 65-nanometre, process technologies, Cadence continues an established track record of innovation by improving its software for power optimisation and analysis, design for manufacturing (DFM), chip-package integration, and design for test (DFT)
This article was originally published on Electronicstalk on 10 Jun 2004 at 8.00am (UK)
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Platforms join new TSMC flow
Both the Encounter digital IC design platform and the Allegro system interconnect design platform have been integrated into TSMC's Reference Flow 5.0.
TSMC integrates nanometre design platforms
The Cadence Encounter digital IC design platform and Cadence Allegro system interconnect platform have been integrated into TSMC's latest reference flow.
This latest milestone in the ongoing collaboration between the two companies delivers an RTL-to-package reference flow to accelerate time to volume for high-performance designs and low-power designs.
The flow delivers a comprehensive methodology to address complex design issues at 65 nanometres, such as tight manufacturing parameters, an exponential increase in leakage power, and new extraction requirements.
Within Reference Flow 7.0, Cadence technologies address these key issues by improving concurrent routing and dual-via insertion, adding new leakage power reduction strategies, addressing process-variation extraction issues, and continuing to optimise package performance and cost.
Further reading
Design flow speeds multi-million-gate design
Advanced Hardware Architectures has designed and taped-out a 10-million-gate forward error correction IC using the 64bit Cadence SP and R design flow.
STMicroelectronics uses Cadence VCC methodology
STMicroelectronics has selected the Cadence Virtual Component Co-Design (VCC) for both its automotive and digital consumer platform system-level design methodology and design flow.
Parasitic extraction technology joins design flow
Cadence Design Systems and Simplex Solutions have signed a technology-licensing agreement that gives Cadence exclusive distribution rights to Simplex Fire and Ice QX.
Also within Reference Flow 7.0, Cadence is for the first time providing a complete RTL-to-GDSII and package flow, including all past and present TSMC Reference Flow capabilities for optimal customer referenceability.
TSMC Reference Flow 7.0 continues to leverage key elements of the Cadence Encounter platform from Reference Flow 6.0, including voltage domain-aware technologies used to create power-gated paths and dynamic-voltage scaling, as well as path-specific power optimisation using fine grain multi-threshold transistors (MTCMOS).
Reference Flow 7.0 expands the range of power optimisation options to include both coarse grain MTCMOS power gating and dynamic-voltage and frequency scaling.
Designers can use these technologies not only to design with multiple supply voltages and power domains, leakage power and de-coupling capacitance optimisation, automatic power-grid generation, and dynamic voltage (IR) drop analysis with actual IC package load models, but also to employ multiple modes of operation within a single block.
The Encounter platform provides a scalable methodology to go from a non-power-domain design to power-domain-based designs, as well as to choose between many options to maximise power optimisation with acceptable area and/or performance.
Complementing this range of power optimisation choices, the Encounter platform in Reference Flow 7.0 allows designers to perform multiple mode/multiple corner timing closure, automatic decoupling capacitor insertion, and dynamic IR analysis, taking into account all power optimisation modes.
Elements of the Encounter platform within Reference Flow 7.0 include Encounter RTL Compiler global synthesis, Encounter Test, SoC Encounter system, Cadence QRC Extraction, VoltageStorm Dynamic Gate power rail analysis, and CeltIC nanometre Delay Calculator (NDC), which work together to deliver high quality of silicon (QoS), improved timing closure, and reduced area.
Cadence SoC Encounter Global Physical Synthesis (GPS), which is included in Reference Flow 7.0, continues to provide solutions for critical manufacturing issues in the IC design process such as wire spreading, double-cut via optimisation and metal fill.
SoC Encounter GPS can automatically insert metal fill into a placed and routed design to achieve a metal density within the range recommended by TSMC design rules.
It also enables automated wire-spreading and double-cut (dual) via insertion, which positively impact yield.
New capabilities in Reference Flow 7.0 include recommended DRC rule routing, half-track wire spreading, and critical area analysis (CAA).
CAA analyses wire density in a design versus defect rate/sise to derive maximum theoretical yield.
SoC Encounter DFY has been certified by TSMC as DFM compliant for CAA.
With Reference Flow 7.0, the Cadence Allegro platform continues the tradition of improving chip/package integration in TSMC Reference Flows such as the new capability of handling simultaneous switching outputs in timing and IR drop analysis.
The flow also includes the capabilities to estimate the ratio of signal to power and ground bumps, estimate the number of vias needed on multiple planes in the package and estimate the number of decoupling capacitors needed in the package.
Encounter Test has been validated by TSMC in Reference Flow 7.0 to address at- speed and power-aware ATPG, at speed-and faster-than-at-speed test, and ATPG test compression.
At 90 nanometres and below, test vectors themselves can cause dynamic IR drop issues during test - indistinguishable at first glance from a failed chip.
Power-aware test allows an understanding of the magnitude and sources of power consumption via toggles in scan flops - thus permitting both re-architecture of test patterns to avoid problems and allowing scan-flop-specific optimisation to reduce power impact.
Faster-than-at-speed test allows testing of the design with a throughput higher than the tester clock rate, while ATPG test compression uses onboard logic to reduce the number of pins and tester-applied vectors needed to achieve test coverage.
A new capability in Reference Flow 7.0 and the Encounter platform is statistical static timing analysis (SSTA) which uses a statistical distribution of cell timing/interconnect variance to determine the statistical distribution of timing of paths as would be expected in silicon.
Cadence QRC Extraction is used to extract parameterised RC as a function of process variations, improving the performance and accuracy for SSTA.
Using the advanced statistical modelling capability of Virtuoso Spectre Circuit Simulator, the process variation information provided by TSMC is accurately simulated and then converted into statistical cell timing models by SignalStorm-LC for statistical timing analysis.
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