Product category:
Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 03 October 2006
Design flow overcomes lithographic
limitations
Cadence Design Systems has created a lithography-aware design flow and has defined an interface that will link resolution enhancement technologies with physical design and verification.
Cadence Design Systems has created a lithography-aware design flow and has defined an interface that will link resolution enhancement technologies (RET) with physical design and verification Cadence has collaborated with Brion Technologies and Clear Shape Technologies in developing this flow which addresses critical lithography-induced yield problems and mask-design challenges
This article was originally published on Electronicstalk on 16 Jul 2008 at 8.00am (UK)
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Design teams can now use the same models throughout the flow across design, implementation and manufacturing, including combining automated layout optimisation with advanced manufacturability models in design phases.
The Cadence interface will be used for the Cadence Encounter digital IC design platform as well as third-party developed design-for-manufacturing (DFM) technologies.
"In keeping with our vision and plan to create a lithography-aware design and implementation flow targeted for challenges at 65nm and below, we've defined an interface that links both internal and external lithography modelling and verification technologies with our design and implementation solutions", said Wei-Jin Dai, Corporate Vice President at Cadence.
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"This design flow is intended for customers who are designing at leading-edge 65, 45 and 32nm processes and those developing lithography-aware DFM flows".
Clear Shape has developed DFM technologies for fast and accurate systematic, full-chip, model-based manufacturing shape analysis for both catastrophic and parametric issues.
Brion Technologies has leveraged its computational lithography technology to deploy an accurate, fast, full-chip optical proximity correction (OPC) and OPC verification solution.
By linking either company's technologies with the Cadence Encounter digital IC design platform including Cadence Chip Optimiser using the newly defined interface, Cadence provides customers with an integrated lithography modelling, design implementation and layout optimisation flow.
The collaborations enable IDMs and fabless semiconductor companies to identify and eliminate lithography hot spots and to optimise both Manhattan and X designs for yield while retaining design and electrical intent.
"As we implement advanced process flows, we see lithography impacts on design becoming more and more critical", said Shuichi Inoue, General Manager, Process Technology Division at NEC Electronics Corporation.
"As a customer of both Brion and Cadence, we're pleased to see this type of collaboration, which enables a lithography-aware design flow that correlates well to the mask-making and manufacturing stages".
"NEC Electronics will help to drive and to provide requirements and directions for this effort".
"Cadence and Brion have collaborated for months to define a lithography-aware design flow that enables our mutual customers to link signoff quality OPC and OPC verification with design stage layout optimisations", said Dr Shauh-Teh Juang, Senior Vice President of Marketing and Business Development at Brion Technologies.
"With 12 of the top 15 semiconductor manufacturers using Brion for OPC or OPC verification, we are seeing the demand for this type of design flow which minimises the risk of costly yield issues".
"We are pleased to be a part of this collaboration with Cadence", said Atul Sharan, CEO of Clear Shape Technologies.
"At sub90nm the industry needs to move from ideal-GDSII based design to true silicon-accurate design".
"Clear Shape has developed unique technologies that enable fast and accurate prediction of silicon in an OPC and RET tool-agnostic manner".
"Our goal is to put DFM solutions that analyse and account for systematic variations on designers' desktops".
"Linking our technologies with Cadence's widely deployed physical design and verification platforms provide designers a plug-in solution that bridges design and manufacturing".
"The new lithography-aware design flow will allow ATI to link manufacturability and design implementation, providing an important element of our robust DFM strategy", said Greg Buchner, Vice President, Engineering, ATI Technologies "By utilising Cadence Chip Optimiser to automatically fix hot spots that are accurately predicted during our physical design phase by Clear Shape's InShape tool, we are able to prevent costly and time-consuming iterations that rely on detecting lithography problems after tape-out or, even worse, in silicon".
"We're encouraged by this type of collaboration and hope to see more situations of companies working together to help solve broader industry problems".
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