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Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Logic Design Team Solution
Edited by the Electronicstalk Editorial Team on 24 October 2006

Teamwork software unifies concurrent
design

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The Cadence Logic Design Team Solution allows concurrent RTL design, enabling schedule predictability.

The Cadence Logic Design Team Solution allows concurrent RTL design, enabling schedule predictability This unique solution equips logic design teams with the elements they need andnot;- from verification and power to test and physical - plus plan-to-closure management and logical signoff - in an integrated and holistic approach

It represents another deliverable in Cadence's overall segmentation strategy, offering tailored solutions for specific types of engineering teams.

Logic design teams are asked to create increasingly sophisticated products in shrinking geometries while meeting a growing range of design objectives, such as correct reusable functionality, power efficiency, functional quality, adequate testability, and physical feasibility among others.

As design complexity has increased, the interdependency of these objectives has grown as well, limiting the scalability of today's manual, sequential and highly iterative approaches.

The result is a growing scheduling "predictability crisis", in which changes made to improve one goal degrade the others, increasing project risks and schedule convergence challenges.

"Time-tomarket pressure combined with growing design complexity offers up many challenges", said Jerry Alston, Senior Vice President at QLogic Corporation.

"The combination of proven integrated front-end verification and implementation technologies for logic-design teams with a seamless linkage to system emulation enables us to stay ahead of the complexity curve".

"Our project teams clearly have an advantage taking this combination of front-end and systems approach, reduced overall product risk, and improved execution from architectural plan to logic design and verification to system-level closure".

The Cadence Logic Design Team Solution integrates technology from the Cadence Incisive functional verification and Encounter digital IC design platforms.

It integrates design, early verification and front-end implementation tasks into a set of objective-focused subflows, and automates the concurrent management of the design's progress toward these objectives.

The solution takes a concurrent 'Design with' approach - with early considerations for interdependencies and iterative flow aspects - as opposed to serial and highly iterative design.

The architecture includes four major elements and an overall plan-to-closure management and logical sign-off solution, while leveraging industry-standard formats such as SystemVerilog.

"At Kawasaki Microelectronics, we rely on Encounter Test technology for the creation and production of deep submicron devices indispensable for the low-power consumer and high-performance information technology markets we serve", said Yoshito Muraishi, Director of CAD Development at Kawasaki Microelectronics: "We are very pleased with the results of the Cadence Logic Design Team Solution, and with its Design with Test aspects".

"The deep level of integration and synergies between testability and synthesis, verification, timing analysis will further accelerate our time to market, reduce design iterations, improve shipped product quality and accelerate yield ramp".

"The schedule predictability crisis is real", said Ted Vucurevich, Senior Vice President and Chief Technology Officer at Cadence.

"We have been aggressively extending front-end technology and methodology innovation, building user-centric integrated flows and solutions across design and verification".

"The Cadence Logic Design Team Solution brings a practical and holistic approach to achieving predictability with an automated concurrent design process, replacing the ad-hoc serial, fragmented and manual approaches of the past".

The Design-for-Test element will be featured at the International Test Conference in San Jose on 24th October 2006.

Elements of the Cadence Logic Design Team Solution are described in more detail in the front-end design white paper on the Cadence website.

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