Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter Test
Edited by the Electronicstalk Editorial
Team on 27 October 2006
Advanced LSI ICs are designed for
testing
NEC uses Encounter Test products to improve the testability and quality of complex devices used in high-end computers developed by the NEC Computers Division.
NEC Corporation is adopting the Cadence Encounter Test products to improve the testability and quality of complex devices used in high-end computers developed by the NEC Computers Division This was made possible by the deployment of Encounter True-Time Test, which identifies small delay defects, commonly present in devices manufactured using advanced process technology and often not detectable with existing test methodologies
This article was originally published on Electronicstalk on 2 Oct 2003 at 8.00am (UK)
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For NEC, improvements in testability and the resulting enhanced quality of their devices translate directly into reduced manufacturing costs and lead time helping NEC satisfy their customers.
This is essential for NEC, which develops some of the world's highest performing supercomputers, highly reliable mainframe products and open servers for a demanding and ever changing market environment.
Encounter True-Time Test technology reduces test escapes which impact product quality.
Further reading
DVD/CD SoC uses Encounter Test Architect
Cadence Design Systems' Encounter Test Architect technology has helped Atmel successfully tape out its first single-chip DVD/CD system-on-chip (SoC).
Timing-aware test generation cuts design delays
Comit Systems has standardised its automatic test pattern generation (ATPG) flow on Cadence Encounter Test.
Diagnostics technology lead extended
Industry-award winning Cadence encounter test expands data compression and yield diagnostic offerings to address escalating manufacturing costs and yield ramp.
Test escapes, measured in defects per million (DPM), are defined as defective devices passing required tests during specific points in the manufacturing process (wafer probe, package test, burn-in etc), but failing later in the manufacturing chain.
These test escapes result in increased costs and lead time for manufacturing products.
To reduce test escapes, Encounter True-Time Test's Timing-Aware ATPG approach tests each potential fault with the tightest possible timing.
The results are highly effective tests that can significantly reduce DPM relative to traditional delay tests.
"In our high-end products, high-quality LSI devices are mandatory in order to reduce costs for material procurement and manufacturing as well to reduce lead time for mass-production".
"It is a fundamental requirement for our NEC Computers Divison to lower DPM by reducing test escapes", said Takayuki Noguchi, General Manager Computers Division, NEC Corporation.
"We are extremely pleased with Encounter Test's ability to improve the quality of our manufacturing methodology".
"Encounter True-Time Test has markedly improved our production effectiveness".
Given NEC's positive results with Encounter True-Time Test, NEC is planning to also adopt Encounter Test compression and Encounter Diagnostics - all key components of the Encounter digital IC design platform.
Encounter Test compression addresses the escalating cost of manufacturing high-quality silicon with a choice of XOR or MISR compression architectures.
The MISR architecture enables superior test-time reduction, while the XOR architecture enables a single-pass diagnostics methodology for newer yield-limited products.
Encounter Diagnostics accelerates yield ramp with its volume and precision modes and its physical-aware diagnostic capabilities - localisation of physical structures within the design that cause yield loss.
"We are delighted to contribute to the quality improvements of NEC's advanced LSI designs", said Sanjiv Taneja, Vice President of R and D for Encounter Test at Cadence.
"Once again, a key customer has validated Encounter Test's unparalleled ability to detect the small delay defects prevalent in leading-edge process technologies".
"We look forward to bringing the full breadth and depth of Encounter Test to NEC enabling them to achieve higher quality, lower cost and faster yield ramp of their devices".
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