Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Cadence incisive palladium III
Edited by the Electronicstalk Editorial
Team on 06 December 2006
High performance enterprise level
verification
Cadence Design Systems has launched the cadence incisive palladium III accelerator/emulator, a high throughput accelerator/emulator
Incisive Palladium III productivity enables high performance enterprise system-level verification Cadence Design Systems has launched the Cadence Incisive Palladium III Accelerator/Emulator, a high throughput accelerator/emulator for verification and validation of complex hardware, software and full systems in the wireless, graphics, networking and consumer markets Palladium III is the first hardware-assisted verification solution to combine high-performance, advanced system-wide automation and management, rapid bring-up, and fast turnaround, for specialists at every level of the system-on-chip (SoC) design chain
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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In addition, Palladium III is fully integrated with the Cadence enterprise system-level (ESL) verification solution, enabling automated and managed hardware, software and full system validation across all engineering design and verification functions.
Palladium III provides up to twice the run-time performance over the previous generation with a vastly superior in the industry debug environment.
With the new system, complex designs can run at speeds approaching 2 MHz, demonstrating up to one million times performance gain over simulation alone.
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Built on Cadence's innovative processor-based technology, Palladium III can serve up to 32 simultaneous users and provides the best compile time in the emulation market with up to 30 million gates per hour on a single workstation and scalable capacity from 1.8 million gates per domain/user to 256 million gates for a full system.
Additional benefits include system-wide management of transaction-based acceleration and assertion-based acceleration with language flexibility.
This flexible environment was developed with a broad range of users in mind by allowing HDL, SystemC, C/C++ and e testbenches, or an external device to interact at high speeds with accelerated designs written in Verilog, SystemVerilog and/or VHDL and assertions written in PSL, OVL and SystemVerilog.
"Enterprise System-Level Verification solutions are becoming critical for our success, and we need to continually strive to shrink our overall verification cycle," said Tom Paulson, principal engineer, QLogic Corporation.
"By comparing Palladium III to the earlier generation, we have seen 3 to 5 times better compile and run-time performance, an order of magnitude debug productivity, and a 3 to 5 times better density providing tremendous throughput".
The Palladium III is a key enabler in the Cadence ESL verification solution by providing constraint-driven, random system-level scenario generation interacting with the accelerated design running in hardware.
Users now have the ability to simultaneously accelerate their SoC designs and embedded processors while automating random testing of embedded software or hardware.
Palladium III users also have the ability to automate and analyse full-system validation and hardware/software co-verification process, as well as track failures and coverage with Incisive Enterprise Manager.
Palladium III enhances system-level debug productivity by accelerating the time it takes to upload waveform information from the hardware to the workstation.
The system uniquely eliminates downtime by offering full interactive visibility to all signals without having to reset the system or the external interfaces.
A new addition to the transaction-based acceleration use model, called concurrent mode, allows the design to run continuously (free running) at full emulation speed, while the testbench is running on the workstation.
This feature combines in-circuit emulation with software testbenches running in Incisive Enterprise Simulator - uniting or adding a transparency layer to the entire system-level verification process.
"Our Palladium series of acceleration/emulation systems continues to raise the bar and deliver the best verification productivity for our customers," said Christopher Tice, senior vice president and general manager of the Verification Acceleration Group at Cadence Design Systems "Palladium III delivers unparalleled performance, superior debug, fast bring-up time and tight integration, with advanced verification automation and management techniques for the world's most complex electronic systems".
The new Palladium III Accelerator/Emulator is available now for beta customers and will be shipped in production in the first half of 2007.
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