Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter RTL Compiler
Edited by the Electronicstalk Editorial
Team on 25 January 2007
Compiler improves timing on large ASIC
blocks
Renesas Technology Corp has adopted Cadence Encounter RTL Compiler with advanced global synthesis in its ASIC design kits and methodologies for 90nm and below.
Renesas Technology Corp has adopted Cadence Encounter RTL Compiler with advanced global synthesis, a key technology of the Encounter digital IC design platform, in its ASIC design kits and methodologies for 90nm and below Renesas is extending its current ASIC kits and methodologies to add support for Encounter RTL Compiler
This article was originally published on Electronicstalk on 19 Feb 2004 at 8.00am (UK)
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Renesas, one of the world's leading semiconductor-solutions providers for the mobile, automotive and PC/AV (audio visual) markets, successfully evaluated Encounter RTL Compiler on large high-performance ASIC blocks.
The resulting blocks achieved greater timing improvement and reduction in area over previously used methodologies.
Renesas has also successfully applied Encounter RTL Compiler's advanced clock-gating optimisation to enable dynamic power reduction and simpler clock-tree.
"Our evaluation of Cadence Encounter RTL Compiler for synthesis of ASIC designs has shown us its value in creating optimised netlists for large and complex designs", said Teruaki Harada, Department Manager, DFM and EDA Technology Development at Design Technology Division, Renesas.
"We have adopted Encounter RTL Compiler for future tapeouts and will now support it for our external ASIC customers".
Encounter RTL Compiler with global synthesis has proven through tapeouts to deliver improved performance, smaller die sizes, lower power consumption, and faster design closure through place and route.
This ability to produce smaller, faster and cooler chips in less time has increased customer competitiveness and reduced overall costs.
Encounter RTL Compiler is available in L, XL and GXL configurations.
"We are pleased that, with the adoption of Encounter RTL Compiler, Renesas is able to achieve design success with large, high-performance ASIC chips", said Nimish Modi, Corporate Vice President, R and D at Cadence.
"Encounter RTL Compiler with global synthesis is a production-proven tool that delivers real business benefits for ASIC customers".
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