Product category:
Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial
Team on 06 February 2007
Design flow adds assertion-based formal
analysis
3Leaf Networks has incorporated the Cadence Incisive Formal Verifier into its overall design flow for assertion-based formal analysis.
3Leaf Networks, a leader in scalable enterprise data centres and virtual servers, has incorporated the Cadence Incisive Formal Verifier (IFV) into its overall design flow for assertion-based formal analysis With this Cadence technology, 3Leaf Networks' logic design teams will introduce assertions into the verification process and begin formal verification early in the design process
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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This will allow 3Leaf Networks to increase its design verification throughput and improve design quality on its complex control blocks by enhancing and streamlining its previous simulation-only verification process.
After initial evaluations of IFV, 3Leaf Networks realised that its logic designers were performing verification weeks or even months prior to simulation.
By working closely with Cadence they were able to get up and running much earlier than predicted, and establish reusable assertion-based verification methods across formal analysis and simulation that has become the foundation for design team verification.
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"As new users of the Incisive Formal Verifier technology and assertion-based verification, we were somewhat surprised to see such dramatic quality and schedule improvements", said Bob Quinn, CEO, 3Leaf Networks.
"Recent complexities have been seriously testing the capabilities of simulation alone".
"IFV brought on a new way of thinking about verification by offering an easy path for our designers to get involved in the process, with the ability to find bugs much earlier".
Part of the Cadence Logic Design Team Solution, Incisive Formal Verifier provides an efficient way to perform early verification.
The technology exposes most functional bugs early in the development of the design, including complex corner-case bugs and protocol compliance violations, while also verifying problem-prone areas.
Other technologies from the Logic Design Team Solution in use at 3Leaf include Incisive Design Team Simulator, Encounter RTL Compiler, Encounter Conformal Equivalence Checker and First Encounter.
"We know how important it is for our customers to get their logic design teams involved in the verification process", said Mitch Weaver, Corporate Vice President, Verification Division, Cadence Design Systems.
"Our successful IFV solution is quickly becoming the cornerstone of design team verification by offering an easy to adopt methodology, resulting in improved project schedules and greater predictability".
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