Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter Conformal Constraint Designer
Edited by the Electronicstalk Editorial
Team on 08 March 2007
Tool detects issues in design
constraints
Faraday Technology Corp uses Encounter Conformal Constraint Designer technology to validate customers' design constraints, ensuring the quality of the design before implementation.
Faraday Technology Corp has adopted Cadence Encounter Conformal Constraint Designer technology for fast, highly reliable signoff of leading-edge designs Faraday uses the Encounter Conformal Constraint Designer technology to validate customers' design constraints, ensuring the quality of the design before implementation
This article was originally published on Electronicstalk on 18 Jan 2005 at 8.00am (UK)
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"Faraday is committed to providing customers with the design expertise and services necessary to bring leading ASIC designs to market", said Kun-Cheng Wu, Director of the Design Development Division at Faraday.
"The Cadence Encounter Conformal Constraint Designer allows us to quickly and easily ensure that our customers' designs are ready for production".
By using the Encounter Conformal Constraint Designer technology as a constraint signoff tool, Faraday is able to detect issues in their customers' design constraints, provide reports on these issues, and allow their customers to correct the constraints early in the design phase.
This signoff procedure improves the quality of Faraday's implementation service while saving both valuable time and resources of its IC design and ASIC customers.
"One of the most important capabilities that we can provide to the design industry is the ability to ensure that design constraints are appropriate and accurate", said Michael Chang, Vice President of R and D for Cadence.
"The Encounter Conformal Constraint Designer technology provides confidence in the integrity of the design, and that's a valuable asset for a design house such as Faraday".
Encounter Conformal Constraint Designer is a key technology in the Cadence Encounter digital IC design platform and a component of the Cadence Logic Design Team Solution.
It enables early logic-design signoff and automates the generation, validation, and refinement of constraints to ensure that timing constraints are valid throughout the entire design process, helping designers achieve rapid timing closure.
Encounter Conformal Constraint Designer is available in L and XL offerings.
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