Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Cadence Encounter
Edited by the Electronicstalk Editorial
Team on 24 April 2007
IC design platform updated
Cadence Design Systems' Cadence Encounter digital IC design platform provides greater ease of use, shorter design time and improved performance for advanced semiconductor design.
Cadence Design Systems has released its latest software version of Cadence Encounter digital IC design platform with industry-leading features including chip optimisation, mixed-signal design support for very large 65nm-and-below designs, diagonal routing using the Encounter X Interconnect option, and support for Si2's Common Power Format (CPF) 1.0-enabled low-power design Available in L, XL and GXL offerings, the new platform provides greater ease of use, shorter design time and improved performance for advanced semiconductor design
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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"The latest release of Encounter platform represents an important development to the members of STARC, because it addresses, in a comprehensive fashion, the challenges inherent in designing for low power and manufacturing, with high productivity", said Nubuyuki Nishiguchi, Vice President and General Manager of STARC.
"This integrated, front-to-back approach creates significant value to leading-edge designers".
A key feature of the latest Encounter platform release is support of the Cadence Low-Power Solution, based on Si2's CPF 1.0 standard.
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The Cadence Low-Power Solution offers a complete flow across logic design, verification, and implementation.
CPF is an industry standard format for specifying power saving techniques throughout the design process, enabling teams to share and re-use low-power intelligence.
In addition, the new release of the Encounter platform provides unparalleled design for manufacturing (DFM) support, yield optimisation, lithography-aware routing, mixed-signal design using new bus routing capabilities, and critical path simulation using the Virtuoso UltraSim Full-chip Simulator.
The platform also features a new power-aware automatic macro placement capability and support for simultaneous multi-mode and multi-corner timing analysis and optimisation.
The Encounter X Interconnect Option delivers higher quality of silicon and cost savings.
"We continue to make significant improvements in Encounter platform to lead the industry in advanced low power and 45/65nm designs".
"The latest developments allow direct benefits to most advanced IC designs", said Dr Chi-Ping Hsu, Corporate Vice President, IC Digital and Power Forward at Cadence.
"This release packs many major breakthroughs - holistic advanced low power, DFM, Encounter X Interconnect Option and mixed-signal design - into a single highly integrated design environment".
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