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Design and Development Software
News Release from: Cadence Design Systems | Subject: 65nm Common Power Format enabled reference flow
Edited by the Electronicstalk Editorial
Team on 25 April 2007
65nm reference flow targets Common
Platform
Cadence Design Systems has released the 65nm Common Power Format enabled reference flow targeting the Common Platform technology.
Cadence Design Systems has announced immediate availability of the 65nm Common Power Format (CPF) enabled reference flow targeting the Common Platform technology This reference flow is the next step in the ongoing collaboration between Cadence and the Common Platform coalition comprised of IBM, Chartered Semiconductor Manufacturing and Samsung
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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Cadence worked closely with the Common Platform technology partners to develop this 65nm flow.
It is based on the Cadence digital IC design platform including Encounter Timing System and CPF to accelerate time to market for low-power system-on-chip (SoC) designs.
"Cadence has worked actively with the Common Platform technology manufacturers to develop this reference flow that enhances our 65-nanometre design enablement portfolio", said Steve Longoria, Vice President of Semiconductor Technology Platform for IBM Global Engineering Solutions.
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"The Common Platform technology companies worked with Cadence engineers to deliver this 65nm reference flow using the ARM-Metro libraries and the Cadence Encounter platform".
"The result is a solution that will bring advanced low-power technology to designers challenged with issues such as battery life and energy conservation in mobile devices and other consumer applications".
This RTL-to-GDSII reference flow is based on the Cadence Encounter digital IC design platform and enables higher productivity and improved quality of silicon (QoS).
The flow addresses critical low-power design challenges, from chip prototyping through power, timing and area optimisation and is targeted for wireless, wireline and consumer applications.
"Collaborating with Cadence is an important part of Samsung's strategy to enable the design chain to bring advanced low-power design methodologies to our foundry customers", said Dr Ben Suh, Vice President, ASIC and Foundry Business Development, System LSI Division at Samsung Electronics.
"This low-power reference flow, targeted to the 65nm LP process, accelerates the time to volume for foundry customers bringing new designs to Samsung for manufacturing".
"We recognise that customers today want solutions to help address power concerns and they want to ensure they have a choice in their solutions".
"In this case, we are working with Cadence and our Common Platform partners to deliver solutions that accelerate designs to silicon while offering customers the flexibility in sourcing options through the collaborative strategy of the Common Platform", said Kevin Meyer, Vice President of Worldwide Marketing and Platform Alliances at Chartered.
"The delivery of this 65nm reference flow makes available an innovative low-power design solution for Chartered customers".
The flow incorporates several innovative technologies in the Encounter platform as well as the Cadence Logic Design Team Solution, including Cadence Encounter RTL Compiler with global synthesis technology, the Cadence SoC Encounter RTL-to-GDSII system, Cadence Encounter Test and Cadence Encounter Conformal Low-Power.
Other Cadence components include VoltageStorm power analysis, and Encounter Timing System using the effective current source model (ECSM) to enable designers to reduce time to volume for low-power consumer applications.
ARM Metro low-power products, part of its family of Artisan physical IP, are used for the flow development.
"ARM and Cadence continue our long-term relationship with ARM Metro low-power IP being an integral component of the reference flow targeting the Common Platform technology", said Tom Lantzsch, Vice President of Marketing, Physical IP, ARM.
"Working with the Common Platform technology partners and Cadence provides manufacturing flexibility along with advanced design solutions to accelerate time to market for our mutual customers".
"Our design chain collaboration with leaders of the Common Platform is what makes new technology like the CPF-based Cadence Low Power Solution a reality", said Jan Willis, Senior Vice President, Industry Alliances, at Cadence.
"This 65nm low-power reference flow provides an integrated methodology for customers to deliver low-power products in volume using CPF with the Common Platform technology".
This 65nm low-power, yield-aware design reference flow is available now.
The reference flow kit contains a reference design, documentation and scripts to run the reference flow.
On Wednesday 13th June 2007 Cadence, Chartered, IBM and Samsung will hold a free webinar on advanced low-power design techniques used in this reference flow.
Further details and registration are available via the Cadence website.
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