Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Incisive Formal Verifier
Edited by the Electronicstalk Editorial
Team on 01 May 2007
Early verification boosts IC design
productivity
Unisys boosts productivity and overall quality, delivering advanced complex chips at multiple sites, by integrating the Incisive Formal Verifier into its design flow.
Unisys Corporation has incorporated Cadence Incisive Formal Verifier (IFV) into its design flow for assertion-based formal analysis Using IFV, Unisys experienced productivity gains and improvements in overall quality, delivering advanced complex chips at multiple sites
This article was originally published on Electronicstalk on 4 May 2005 at 8.00am (UK)
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Part of the Cadence Logic Design Team Solution's "design with verification" approach, IFV exposed many hard-to-find functional bugs early in the Unisys design cycle, enabling greater team productivity and accelerating project completion.
Logic designers were able to verify design blocks months prior to testbench simulation, resulting in faster and more cost-efficient overall chip verification.
Moreover, the assertions developed by the team early in the design cycle were fully reusable in simulation and acceleration/emulation later in the flow, adding greater observability and leading to faster debug and an overall shorter verification cycle.
"Design with verification starting with Incisive Formal Verifier has helped us take our enterprise servers to market more efficiently and earlier, and at a lower cost", said Steve Guarrieri, Vice President of Platform Development at Unisys.
"In addition, it helped mitigate the risk of corner-case respins, and we've found it easy to broadly deploy into our standard product flow across multiple projects, including our most advanced and complex ASICs".
The Unisys team reported success on multiple projects, including a highly complex ASIC design.
The ease of adoption and designer-friendly nature of the IFV technology further enhanced the Unisys verification environment that included Incisive Design Team Simulator and Incisive Palladium emulator.
When combined with the comprehensive plan-to-closure assertion-based verification methodology, Unisys realised significant productivity gains.
"We are excited to see companies such as Unisys, reaping savings and benefits from the Cadence Logic Design Team Solution's early verification technology", said Steve Glaser, Corporate Vice President of Marketing, Verification Division at Cadence.
"Incisive Formal Verifier offers a complete plan-to-closure assertion-based verification methodology, yields tremendous productivity and quality gains, and provides a perfect fit for design teams that want to optimise RTL bring-up and improve overall project time to market".
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