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Design and Development Software
News Release from: Cadence Design Systems | Subject: Low-Power Methodology Kit
Edited by the Electronicstalk Editorial
Team on 16 May 2007
Kit cuts the cost of low-power IC design
Design kit enables engineers of different experience levels to adopt advanced low-power techniques with minimal risk and deployment effort.
Cadence Design Systems has announced the industry's first kit that enables engineers of different experience levels to adopt advanced low-power techniques with minimised risk and deployment effort A complement to the Cadence Low-Power Solution, the Cadence Low-Power Methodology Kit provides a working end-to-end methodology covering logic design, functional verification and physical implementation
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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The Kit includes example IP, scripts and libraries; all proven on an included wireless segment representative design.
Delivered together with Cadence applicability consulting services, the kit enables design teams without extensive low-power implementations to quickly optimise their low-power design environment, and accelerate their time to lower power, more competitive system-on-chip products.
The Cadence Low-Power Methodology Kit contains a generic wireless application design, implemented using multiple-supply-voltage and power-shut-off methods, and all associated command scripts and technology files needed to carry the design through the entire end-to-end flow.
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The example IP in the design is from Cadence and third parties including ARM processor and Amba on-chip communication technology, Wi-Fi from Wipro, USB 2.0 from ChipIdea, 65nm ultra-low-power memories from Virage Logic and 65nm technology libraries from TSMC.
"The Cadence Low-Power Methodology Kit allowed us to reduce the turnaround time for implementing and verifying a low-power solution for our design", said Dr Samuel Sheng, CTO of Telegent Systems.
"The kit simplified both the logical and physical implementation for our design; we plan to use it in our future tape outs".
"Having access to such kits is a great benefit as they allow users to leverage and adapt proven solutions quickly and with minimal risk".
"The semiconductor industry needs to speed up deployment of low-power methods", said Craig Johnson, Corporate Vice President for Marketing and Strategy at Cadence.
"The systems markets, especially wireless and consumer, demand it".
"While some IC companies have already completed large numbers of sophisticated low-power tapeouts, many others are still tuning or even establishing their infrastructure and knowhow".
"The Cadence Low-Power Methodology Kit directly addresses this problem; it helps low-power teams deploy optimised, highly automated low-power design flows quickly across multiple engineering groups for maximum productivity".
The Low-Power Methodology Kit is modular and includes six distinct flows: low-power functional simulation, logic synthesis, design for test and ATPG, physical design, formal implementation, verification and power grid signoff.
Users can implement the entire Kit as an integrated flow, or may select modules individually.
The Si2 Common Power Format standard is used to provide a single specification of low-power intent throughout the flow.
"Power has become a critical success factor for our customers and a key differentiator for our communication IP, like our 802.11 WiLD IP that Cadence embedded in its kit", said Mana Coste, Director Marketing for Wipro-NewLogic.
"We are pleased to see Cadence take the lead in the industry, enabling delivery of easily integrated low-power IP solutions".
"Integration and reuse of IP in a low-power environment creates new challenges not easily solved using traditional approaches for our customers and their design processes", said Ian Drew, Vice President, Segment, ARM.
"Through the kits initiative, Cadence is directly addressing these challenges, which support our mutual customers".
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