Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Incisive
Edited by the Electronicstalk Editorial
Team on 30 May 2007
Methodology combines design with
verification
Fujitsu Kyushu Network Technologies is using the Cadence Incisive plan-to-closure methodology for SystemVerilog verification in RTL logic design teams.
Fujitsu Kyushu Network Technologies is using the Cadence Incisive plan-to-closure methodology for SystemVerilog verification in RTL logic design teams The Cadence methodology was recently used to verify Fujitsu's latest set of MPEG decoder modules delivering motion block decoding capabilities
This article was originally published on Electronicstalk on 26 Feb 2003 at 8.00am (UK)
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It includes a proven multilanguage approach to verification reuse and specifically targets logic designers who need "design-with-verification" capabilities that ease SystemVerilog adoption.
Based on feedback from recent projects, Fujitsu found that adoption of the plan-to-closure methodology was very practical for designers needing advanced verification capabilities and also demonstrated the scalability needed to leverage SystemVerilog-based environments from individual modules to full systems.
The ability to perform automated functional coverage analysis and checking sped the verification process and cut the overall verification time by nearly half.
The methodology also ensured that the design was of the highest quality before taping out.
"Our logic designers found bugs much earlier with the Cadence SystemVerilog-based methodology", said Takahiro Kobayakawa, Senior Engineer at Fujitsu Kyushu Network Technologies.
"It has offered our designers an easy-to-adopt automation layer that allows much more control and insight into the verification process".
The team also realised other benefits, including easy integration of existing C-based Verilog functions into the SystemVerilog test environment, which allowed efficient re-use of proven verification code.
This also saved the team a compile step further compressing the verification cycle.
"We're delighted that our solutions have lowered the adoption bar for designers who need SystemVerilog-based solutions", said Steve Glaser, Corporate Vice President, Marketing, Verification Division at Cadence.
"We'll continue to carve out a practical path for logic design teams to implement 'design-with-verification' approaches to ensure high quality throughout the design process, from module to full system level".
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