Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial
Team on 01 June 2007
Design platform enable DDR integration
at 65nm
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform.
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform This new methodology uses Cadence SoC Encounter RTL-to-GSDII system for design and physical implementation and Cadence Encounter Timing System for design closure and final timing, signal integrity and signoff - both are key technologies of the CPF-enabled Encounter platform
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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Toshiba America Electronic Components (TAEC) has successfully implemented an 8-million-gate SoC using the Cadence Encounter digital IC platform.
Signal integrity tool spots damaging glitches
Cadence Design Systems has made significant enhancements to its CeltIC 4.1 signal integrity solution, a key technology of the Encounter digital IC design platform for nanometre-scale IC designs.
Using the combination of Denali's Databahn DDR controller and PHY IP with the Encounter technologies, customers can now achieve DDR memory-system implementations at 65nm and at speeds exceeding 400MHz.
"DDR-PHY implementation had become one of the top problems for our customers", says Brian Gardner, Vice President of IP products at Denali.
"When we set out to solve this problem, we quickly realised the need for high-quality tools that provide a consistent view of timing, signal integrity, and power throughout the design and physical implementation process".
Further reading
Encounter speeds Wintegra's nanometre designs
Wintegra has deployed the Cadence Encounter digital IC design platform to take the next step into the challenge of nanometre design technology.
RTL compiler synthesis speeds multicore design
Toshiba America Electronic Components has used the Cadence Encounter digital IC design platform with nanometre synthesis technology to deliver a 530MHz synthesisable 64bit dual-issue MIPS core.
Editor finishes the job in record time
The Virtuoso Chip Editor chip finisher uses the OpenAccess application programming interface and database to directly link the Encounter digital platform with the Cadence custom environment.
"Using SoC Encounter and Encounter Timing System, we were able to put together a complete system solution for DDR-PHY development that enables customers to achieve higher-quality designs, in less time, and with minimised risk".
"Cadence was the obvious choice for selecting a partner to solve this problem".
This methodology combines innovative design techniques, and world-class implementation and analysis solutions enabling robust customer design kits, or complete IP hardening leading to the market's smallest and highest performance configurable DDR-PHY products.
An estimated 70% of new SoC designs use DDR-memory-subsystem IP.
DDR memory systems with superior system-performance requirements have become a critical factor for products in the networking, computing, and consumer-electronics segments where memory bandwidth is a critical factor for achieving system performance.
Additionally, due to dramatic increase in clock speeds and the storied challenges of 65-nanometre implementation, the ability to implement DDR-PHYs and quick closure on timing has become a serious bottleneck to time to market.
Some of the world's largest IDMs have declared this as their number one problem.
After careful evaluation, Denali has standardised on SoC Encounter and Encounter Timing System for superior DDR-PHY design, physical implementation, timing closure, and signoff analysis.
With this solution, Denali now delivers proven design kits, methodology services, and hardened IP to its customers.
"We are very pleased to be working with Denali, a recognised leader in memory systems and IP that are deployed in a wide scope of end applications ranging from mobile phones to world-class routers", said Dr Chi-Ping Hsu, Corporate Vice President, IC Digital and Power Forward at Cadence.
"The Denali DDR controller and PHY IP represent an optimal solution that offers a wide range of programmability and configurability".
"The Cadence Encounter platform together with Si2's CPF and the Denali DDR-PHY methodology provides a uniquely powerful and flexible solution that comprehensively addresses power, performance, and time to market challenges of today's SoC designs".
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