Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter Timing System
Edited by the Electronicstalk Editorial
Team on 28 June 2007
Timing system is integral part of
tapeout success
Atheros Communications has used Cadence Encounter software to design its new AR9001 series of 802.11n chipsets.
Atheros Communications has used the Cadence Encounter Timing System for power signoff and Encounter RTL Compiler with global synthesis and physical layout estimation (PLE) to design the new Atheros AR9001 series of 802.11n chipsets The AR9001 offers Atheros customers a wide range of price, performance and form factors, enabling fast penetration of the growing 802.11n market
This article was originally published on Electronicstalk on 6 Sep 2006 at 8.00am (UK)
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Fujitsu has adopted the Cadence Encounter Timing System for timing analysis in its implementation flow.
The Encounter Timing System is the most complete and integrated electrical signoff environment for faster optimisation, debug and final verification for timing and signal integrity with power - a key requirement for Atheros and other leading design companies.
With the Encounter Timing System, Atheros' engineers were able to gain time to market and achieve significantly increased productivity from having a common electrical view of their design throughout the flow, and a robust debug environment for rapid diagnosis of multidimensional and interdependent timing-closure issues.
The same signoff-quality analysis is also used throughout their entire Cadence SoC Encounter RTL-to-GDSII system, thereby preventing unnecessary front-to-back iterations to reconcile timing mismatches, and enabling fast design closure.
Further reading
Design flow speeds multi-million-gate design
Advanced Hardware Architectures has designed and taped-out a 10-million-gate forward error correction IC using the 64bit Cadence SP and R design flow.
STMicroelectronics uses Cadence VCC methodology
STMicroelectronics has selected the Cadence Virtual Component Co-Design (VCC) for both its automotive and digital consumer platform system-level design methodology and design flow.
Time to market is extremely critical for wireless consumer chips and the AR9001 made it more challenging with its increased integration and performance targets.
The consistency of timing and signal integrity views, from implementation through final Encounter Timing System signoff, significantly accelerated the AR9001 design closure, and enabled Atheros to meet an aggressive tapeout schedule.
"Encounter Timing System is an integral part of the tapeout success of our AR9001 system-on-chip solution, which combines a wireless network processor and a BB/MAC in a single Wi-Fi chip", says Steve Padnos, Methodology Architect at Atheros.
"Encounter Timing System in conjunction with Cadence Encounter RTL Compiler with global synthesis and physical layout estimation helped us achieve the industry's highest performance, dual-concurrent router design setting a new 802.11n performance benchmark".
"The performance of Encounter Timing System and the ease of migration made our adoption very easy".
"With the Cadence Encounter Timing System, Atheros enhanced the development process of their latest AR9001 802.11n networking solutions", says Eric Filseth, Corporate Vice President, IC Digital Marketing at Cadence.
"As this case shows, Encounter Timing System enables companies such as Atheros and their customers to realise significant benefits and savings through productivity and quality gains, as well as improvements to design optimisation and overall project time".
Encounter Timing System and Encounter RTL Compiler are components of Cadence Encounter digital IC design platform and Cadence Logic Design Team Solution.
Encounter Timing System is available in L and XL offerings; Encounter RTL Compiler is available in L, XL and GXL.
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