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Design and Development Software
News Release from: Cadence Design Systems | Subject: Logic Design Team Solution
Edited by the Electronicstalk Editorial
Team on 10 July 2007
Logic designers get physical with
floorplan data
"Design with physical" approach automatically delivers an accurate physical description of the design into the logic design stage.
Cadence Design Systems has come up with an innovative solution to the crucial challenge of achieving timing, power, area and schedule predictability in the handoff of complex semiconductor designs from logic design teams to physical implementation teams The Cadence Logic Design Team Solution offers a new "design with physical" approach that resolves this conundrum by automatically delivering an accurate physical description of the design into the logic design stage
This article was originally published on Electronicstalk on 24 Oct 2006 at 8.00am (UK)
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As a result, logic design teams now can automatically design and synthesise with real physical floorplan data, virtually eliminating disparities between logical and physical timing views, resulting in increased design quality and improved physical predictability, faster closure and improved quality of silicon (QoS) in timing, area, and power.
Physical timing effects have become more significant with each new process generation, yet a gap has remained between logical and physical views of a design.
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This causes numerous, lengthy iterations between logical and physical design teams to achieve design goals.
Up to now, logic designers attempted to circumvent this problem by increasing timing margins, but this results in unacceptable increases in die size and power consumption.
The Cadence Logic Design Team Solution solves this conundrum by replacing traditional statistical wireload models with real physical timing information.
The RTL-to-gate transformation and optimisation process is driven by a proprietary Physical Layout Estimation (PLE) algorithm in Encounter RTL Compiler that's been proven in over 100 tapeouts to create a better, pre-converged netlist for implementation.
Then, in a new and unique approach, the First Encounter silicon virtual prototyping capability is incorporated into the synthesis cockpit to quickly obtain the most accurate view of physical interconnect timing.
The combination of physical layout estimation algorithms and embedded silicon virtual prototyping technologies create a comprehensive interconnect modelling strategy that spans from RTL to gate level and accurately models both long and short wires.
This all but eliminates disparities between logical and physical timing views, virtually eradicating schedule-killing, big-loop iterations and the need to over-margin timing at the cost of power.
"This breakthrough solution provides logic design teams with an automated method to ensure accurate timing closure without lengthy iterations with the physical implementation team - a powerful capability that greatly improves the predictability of the design schedule and dramatically increases the quality of silicon", says Nimish Modi, Corporate Vice President of Front End Design at Cadence.
"It's based on new ways of using proven technologies together to generate superb results".
"This is another case where the Cadence Logic Design Team Solution is delivering tangible benefits to logic designers by looking at the problem with a holistic solution".
The Cadence Logic Design Team Solution helps logic design teams improve schedule predictability through plan-to-closure management and logical signoff, in an integrated and holistic approach covering both design and verification.
It is another example of how Cadence offers tailored solutions for specific types of engineering teams.
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