Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Cadence Encounter
Edited by the Electronicstalk Editorial
Team on 11 September 2007
IC platform cuts design times
Cadence's new approach directly models critical elements of the manufacturing process instead of relying on conservative design rules.
Cadence Design Systems has released a set of design products and capabilities for faster production of digital system-on-chip (SoC) designs Cadence will exhibit its 45nm design flows to semiconductor designers and design at the CDNLive! Silicon Valley user conference
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
Related stories
Digital IC platform sorts out 8-million-gate SoC
Toshiba America Electronic Components (TAEC) has successfully implemented an 8-million-gate SoC using the Cadence Encounter digital IC platform.
Encounter speeds Wintegra's nanometre designs
Wintegra has deployed the Cadence Encounter digital IC design platform to take the next step into the challenge of nanometre design technology.
Version 7.1 of the Cadence Encounter digital IC platform is scheduled for release in October.
"At aggressive geometries, traditional design flows no longer provide accurate predictability, forcing designers to either guardband their designs excessively, or risk manufacturability problems", said Mike McAweeney, Vice President of DFM Marketing at Cadence.
"By modelling key manufacturing processes within the implementation flow and optimising early, we're reducing overall design time and improving designers' confidence that the chip will work as intended".
Further reading
RTL compiler synthesis speeds multicore design
Toshiba America Electronic Components has used the Cadence Encounter digital IC design platform with nanometre synthesis technology to deliver a 530MHz synthesisable 64bit dual-issue MIPS core.
Design platform speeds DSL chipsets to market
DSL chipset provider Metalink has deployed the Cadence Encounter digital IC design platform to meet the intensive design challenges of nanometre technology.
Platform speeds into nanometre design
Version 3.2 of the Cadence Encounter digital IC design platform delivers enhanced timing optimisation, placement and other technology for very large, fast ICs.
"With this approach, Cadence is providing a 'what you design is what you get' capability which brings manufacturing predictability back to the designer".
A standard IC design consideration has long been manufacturing variability, which can result in both catastrophic and parametric yield failures.
Traditionally, these failures were avoided through conservative "physical design rules", which prevented the implementation flow from creating any structures deemed risky.
However, at advanced technology nodes of 65nm and especially at 45nm and below, the necessary "rules" are so conservative as to significantly limit IC performance and unnecessarily increase die area - and still may not avoid all problems.
With this announcement, Cadence establishes a new approach to advanced process node design which addresses this challenge by going beyond "rules" and directly modelling critical elements of the manufacturing process and using the models to produce a DFM-correct design through a prevention, analysis and optimisation sequence.
To prevent lithography violations in SoC applications, the Cadence NanoRoute router adds new technology which avoids gross lithography errors during routing for an immediate 50-80% reduction in lithographic "hotspots".
Cadence Encounter QRC Extraction has been enhanced to support the advanced process models for accurate statistical parasitics extraction.
For custom applications, a new capability of the Cadence Virtuoso custom design platform leverages "recommended" rules as a starting point for further analysis and optimisation.
Accurate lithography analysis is accomplished using the Cadence Litho Physical Analyser, formerly known as InShape from Clear Shape Technologies and recently acquired by Cadence.
Any remaining lithography hotspots are optimised using a combination of grid and space-based methods, the latter of which enables extremely fine-grained optimisation and interconnect refinement.
The end result of this approach is a design which does not require excessive lithography correction during the photomask phase manufacturing - it is essentially correct already.
CMP and random variation are managed through similar approaches, using the new Cadence's CMP Predictor analysis, and optimised through intelligent metal-fill and multicorner timing optimisation methods.
Cadence supports a suite of final analysis technologies that ensure the design will perform correctly after manufacturing.
Critical lithography and CMP elements are analysed using Cadence Litho Physical Analyser and CMP Predictor.
For timing analysis, a new statistical timing analysis system is being added to the Cadence Encounter Timing System GXL.
Encounter Timing System GXL offers two significant advantages over the conventional multicorner timing analysis used in most 65nm design flows.
It avoids the pessimism associated with "corners", many of which represent cases which are theoretically possible but increasingly unlikely.
Encounter Timing System GXL also executes in a fraction of the time usually required to analyse timing on large sets of scenarios.
"Process variation is a major problem for our members doing sub-65nm designs, where today's corner-based design flows are too pessimistic leading to lower chip performance", said Nobuyuki Nishiguchi, Vice President and General Manager of Development Department 1 of Japan's Semiconductor Technology Academic Research centre (STARC).
"We have been working with Cadence Encounter statistical timing analysis, optimisation, and characterisation for over a year and we are confident in its ability to deliver superb quality of results and yield improvement".
"Our exhaustive testing has proven that the Encounter statistical timing analysis is fast and accurate, and its seamless integration into the Encounter sign-off analysis and implementation environments makes it the most complete statistical timing technology available".
Cadence Litho Physical Analyser, CMP Predictor, Cadence Encounter QRC Extraction and Encounter Timing System GXL are supported in leading foundry flows including the TSMC 8.0 Reference Flow.
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
