Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial
Team on 26 September 2007
Statistics prevent catastrophic silicon
failures
Advanced statistical timing analysis and optimisation technology allows Renesas to accurately account for the effects of process variability in its leading-edge 45nm digital designs.
Renesas Technology Corp has adopted statistical static timing analysis (SSTA) technology from the Cadence Encounter digital IC design platform as part of its next-generation design flow This advanced statistical timing analysis and optimisation technology - an integral part of the Cadence Encounter Timing System and SoC Encounter RTL-to-GDSII System - allows Renesas to accurately account for the effects of process variability in its leading-edge 45nm digital designs
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
Related stories
Digital IC platform sorts out 8-million-gate SoC
Toshiba America Electronic Components (TAEC) has successfully implemented an 8-million-gate SoC using the Cadence Encounter digital IC platform.
Signal integrity tool spots damaging glitches
Cadence Design Systems has made significant enhancements to its CeltIC 4.1 signal integrity solution, a key technology of the Encounter digital IC design platform for nanometre-scale IC designs.
The benefits include reduced silicon-failure risk, improved design robustness and convergence, enhanced quality of silicon (QoS), significantly faster turnaround time and a streamlined signoff flow.
Variations in manufacturing result in structural changes in devices and interconnects, leading to deviations in their electrical behaviour.
At 65nm and below, process control is difficult and, as a result, designs that pass traditional signoff standards might fail in silicon due to process variations.
Further reading
Encounter speeds Wintegra's nanometre designs
Wintegra has deployed the Cadence Encounter digital IC design platform to take the next step into the challenge of nanometre design technology.
RTL compiler synthesis speeds multicore design
Toshiba America Electronic Components has used the Cadence Encounter digital IC design platform with nanometre synthesis technology to deliver a 530MHz synthesisable 64bit dual-issue MIPS core.
Editor finishes the job in record time
The Virtuoso Chip Editor chip finisher uses the OpenAccess application programming interface and database to directly link the Encounter digital platform with the Cadence custom environment.
The SSTA technology from Cadence helps prevent these catastrophic silicon failures.
Traditional timing analysis accounts for process variations by introducing more aggressive gross guard-band and multiple analysis corners to model different process and environmental variation combinations.
Encounter Timing System GXL supplements traditional corner-based methods with powerful and accurate SSTA technology that can account for the variability of process parameters in a single run.
"At advanced technology nodes, statistical timing analysis is necessary to eliminate excessive over-design while maximising performance, and to allow trade-offs between performance, yield and price", says Hisaharu Miwa, General Manager, Design Technology Div, LSI Product Technology Unit at Renesas Technology Corp.
"Over the course of nine months, we performed rigorous evaluations of all commercial SSTA solutions on the market using comprehensive evaluation criteria".
"The SSTA technology in the Cadence Encounter platform scored the highest with a winning combination of speed, accuracy, and timing optimisation capabilities".
"Also, since it communicates smoothly with the Encounter implementation flow and accurately accounts for inter-die, within-die and intracell variations, it will help us to accelerate timing closure and signoff".
The Encounter platform's fast and accurate SSTA and concurrent optimisation technology correctly accounts for how process variation affects delay and leakage power.
This allows design engineers to move beyond the artificial limitations on speed, area and power imposed by a traditional corner-based approach.
The SSTA technology holistically models the effect that global, within-the-die, and random variations have on delay while significantly reducing the pessimism that causes traditional design methodologies to break down below 65nm.
The net result is fewer analysis corners, increased chip performance and better silicon.
"With Statistical STA technology, Renesas designers will be able to unlock the true potential of smaller process technologies in their next generation flow", says David Desharnais, Product Marketing Group Director, Encounter.
"Moving to smaller technologies, especially below 65nm, can be risky".
"The SSTA technology in Encounter Timing System GXL can relieve much of the pain for customers, such as Renesas, empowering them to maximise design performance with minimum power consumption".
SSTA is available as part of Encounter Timing System GXL and SoC Encounter GXL system.
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
