Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial
Team on 27 September 2007
Multicore design optimises ARM
performance
Design success prompts NEC to standardise on the Encounter platform as its tapeout methodology of choice for ARM processor implementations.
NEC Electronics America has used the Cadence Encounter digital IC design platform to implement one of the world's highest-performance low-power ARM11 MPCore multicore processors The success of the dual core implementation of the ARM11 MPCore processor core, rated at over 700MHz and built on 90nm process technology, has prompted NEC to standardise on the Encounter platform as its tapeout methodology of choice for ARM processor implementations
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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"Previous tools could not achieve our performance objectives".
"The Cadence Low-Power Solution, including Encounter RTL Compiler and SoC Encounter GXL, allowed us to actually exceed our performance target of 700MHz", says Ying F Chang, Engineering Director, Design Solutions centre of NEC Electronics America.
"This important development allows us to offer differentiated, performance-optimised lower-power embedded processors to our customers".
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As the result of this development, and after extensive additional qualifications, NEC has now standardised its tapeout methodology on Cadence Encounter RTL Compiler global synthesis and the Cadence SoC Encounter GXL RTL-to-GDSII system for ASIC designs using ARM processors in various combinations of low-power and high-performance libraries.
Importantly, the use of Cadence tools allowed NEC to achieve overall improvements in timing performance and lower power consumption for its ARM11 MPCore processor implementation while still adhering to its electromigration rules - an objective that was not met through competitor tools.
"This implementation of the ARM11 MPCore is the latest result of a joint agreement between ARM and NEC in 2003 to develop and promote high-performance multiprocessor solutions based on the ARM11 microarchitecture", says Eric Schorn, VP Marketing, Processor Division, ARM.
"The partnership between ARM and Cadence has enabled NEC to deliver a very competitive ARM processor-based multicore processor solution that will enable OEMs to meet the stringent performance and power consumption requirements of next-generation high-volume applications".
"NEC uses ARM11 processors in many ASIC projects".
"The company's ability to achieve the aggressive power and performance requirements of its customers is vital to its success", says Mike McAweeney, Vice President of Marketing at Cadence.
"This switch to the Cadence Encounter platform provided a clear demonstration of Cadence technologies' high-end digital solution, and its advanced implementation capabilities for ARM processors".
"Furthermore, the Cadence Encounter platform was able to adapt stringent new electromigration rules into the low-power methodology without impact to performance or power consumption".
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