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Design and Development Software
News Release from: Cadence Design Systems | Subject: Cadence Encounter Test solution
Edited by the Electronicstalk Editorial
Team on 24 October 2007
Software spots chip flaws
The Cadence Encounter Test solution was able to help IBM meet its goals for quality and volume production.
Cadence Design Systems has helped IBM deliver high-quality, high-volume chips for consumer devices by enabling the detection and correction of "small delay defects", miniscule defects that are nearly invisible without sophisticated test programs that operate above the normal operating speed of the chip Most recently, the Cadence Encounter Test solution was able to help IBM meet its goals for quality and volume production of a high-performance custom chip based on IBM's Power Architecture technology
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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To address this problem, IBM is working with Cadence Design Systems' Encounter Test group.
"The Cadence Encounter Test team has a capability called small delay defect detection", said Ron Martino, Director of Power Architecture, IBM Global Engineering Solutions.
"What this means is, they can detect a timing delay in a signal that is caused not by a broken wire, but by one that is merely a few atoms thinner than it is supposed to be".
"The difference in thickness creates a difference in resistivity, which delays the signal for a fraction of a nanosecond".
"In many high-performance, high volume applications, that's just too long".
Traditional test methodologies using test vectors can overlook such small delays, enabling test escapes that eventually manifest themselves as consumer product failures.
Cadence Encounter Test avoids this problem through Encounter True-Time Test, which accelerates the speed of the device to reveal very small timing delays, much as running an automobile engine at a high rev/min will reveal performance issues that would not show up at a lower speed".
"By using the Encounter True-Time Test capability, IBM was able to assure extremely low defect rates for a superscalar chip design", said Sanjiv Taneja, Vice President of Encounter Test R and D at Cadence".
"This was important for IBM, it's important for their customer, but most of all, it's important for users of high-performance systems, because it demonstrates that there are ways to enable higher quality even as the semiconductor industry moves to smaller and more complex technologies".
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