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News Release from: Cadence Design Systems | Subject: ARM reference methodologies
Edited by the Electronicstalk Editorial
Team on 07 December 2007
Reference methodologies speed ARM design
Methodologies for two ARM processors provide enhanced design solutions to mutual customers designing multicore, low-power devices.
Cadence Design Systems and ARM have developed two new implementation reference methodologies: one for the ARM11 MPCore multicore processor and the other for low-power implementation of the ARM1176JZF-S processor, which incorporates ARM Intelligent Energy Manager (IEM) technology These Cadence reference methodologies for the two ARM processors are the result of close collaboration between the two companies, and provide enhanced design solutions to mutual customers designing multicore, low-power devices
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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"The reference methodology for the ARM11 MPCore multicore processor provides a high-performance reference flow that offers predictable, low-risk implementation of multiprocessor configurations", says Keith Clarke, Vice President of Technical Marketing at ARM.
"Both the ARM11 MPCore processor and low-power ARM1176JZF-S processor flows have been prevalidated with ARM Artisan Physical IP in order to optimise the implementation of ARM synthesisable processor IP".
The low-power reference methodology for the ARM1176JZF-S processor provides enhanced features required to support IEM technology, which has been shown to reduce CPU energy consumption by more than 60%, and supports the Dynamic Voltage and Frequency Scaling (DVFS) hardware technique that IEM technology exploits.
The reference methodologies comprehend the Common Power Format (CPF), which enables the up-front specification of power domains, power modes, level shifting and isolation rules to automate advanced low-power design techniques.
The methodologies leverage a wide range of products of the Cadence Low-Power Solution, including the Cadence SoC Encounter RTL-to-GDSII system, Encounter RTL Compiler with global synthesis, Encounter Conformal Low Power and VoltageStorm power rail analysis.
"These jointly developed reference methodologies offer significant benefits in multiprocessing and power consumption for customers designing the next-generation consumer devices which require performance and superior power management", says Mike McAweeney, Vice President, Product Marketing at Cadence.
"Use of the reference methodologies by engineering teams helps reduce time to tapeout of customised designs, thereby gaining considerable time to market and cost benefits".
ARM and Cadence, a member of the ARM Connected Community, will leverage their extensive experience gained in developing these advanced flows for low-power and multiprocessing applications in the development of new reference methodologies for the latest ARM processors, the Cortex A9 processor and the ARM Cortex-A9 MPCore multicore processor.
These reference methodologies are planned to be available at the time of the production release of these new processors in the first half of 2008.
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