Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Open Verification Methodology
Edited by the Electronicstalk Editorial
Team on 11 January 2008
Open-source software standardises
verification
The OVM is the first open language-interoperable SystemVerilog verification methodology in the industry.
Cadence Design Systems and Mentor Graphics Corp have announced immediate availability of the Open Verification Methodology (OVM) Distributed under the standard open-source Apache 2.0 licence, the OVM source code, documentation and use examples may be downloaded free of charge
This article was originally published on Electronicstalk on 15 Feb 2008 at 8.00am (UK)
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The OVM, based on the IEEE1800-2005 SystemVerilog standard, is the first open, language interoperable, SystemVerilog verification methodology in the industry.
The OVM provides a methodology and accompanying library that allow users to create modular, reusable verification environments in which components communicate with each other via standard transaction-level modelling interfaces.
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It also enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows.
As a joint development initiative between Mentor Graphics and Cadence Design Systems, the OVM is supported on multiple verification platforms ideally suited to both novice and expert verification engineers.
"Open source, plug-and-play reuse, and multilanguage support are the leading requests from our verification and training customers", said Yoshifumi Nagano, CEO of hd Lab.
"We have reviewed other methodologies in the market, but only OVM offers this combination of capabilities".
"We are pleased to see the first release of the OVM source code and believe this will increase our efficiency".
The OVM includes the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments and reusable verification IP (VIP) in SystemVerilog.
The OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library, and significantly shortens the time to create verification environments.
It easily integrates plug-and-play VIP and ensures code portability and reuse.
"As a leading supplier of silicon IP, Denali is pleased to see the significant traction OVM has gained throughout the industry", says Juirong Cheng, Vice President of engineering at Denali Software.
"The OVM 1.0 achieves the fusion of open SystemVerilog and interoperability required to enable adoption across our broad customer base".
"The OVM source code, documentation, and examples have the quality and interoperability we need to deliver OVM-compliant VIP this year".
"The Open Verification Methodology represents a major step forward in protecting our customers' investment in verification flows and reusable verification IP", says Robert Hum, vice president and general manager of Mentor Graphics Design, Verification and Test Business Unit.
"After extensive customer interaction, we believe OVM will definitely accelerate the move to SystemVerilog, and provide significant competitive advantage to design and verification teams around the world".
"We have discussed OVM with more than a thousand engineers at customer sites and have worked with more than a dozen customers and partners during the beta period", says Ziv Binyamini, Corporate Vice President, Product and Technologies Organisation at Cadence Design Systems.
"The level of interest in OVM is overwhelming, so we are pleased to be able to make it available to the entire industry as a critical step in delivering on the full promise of SystemVerilog".
"Doulos is pleased to be associated with the first public release of OVM, and to have worked closely with the Cadence and Mentor teams to ensure OVM adopters have access to high-quality training aligned with this release", says Rob Hurley, CEO of Doulos.
"OVM addresses the very real market need for a standard verification methodology based on SystemVerilog, and does so in style".
A production version of OVM is available immediately with additional functionality planned for release later in 2008.
Cadence and Mentor have collaborated to ensure that the OVM runs on their simulators and enables backwards compatibility with their existing environments, Advanced Verification Methodology from Mentor Graphics, and Incisive Plan-to-Closure Methodology (Universal Reuse Methodology module) from Cadence.
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