Product category:
Design and Development Software
News Release from: Cadence Design Systems | Subject: Virtuoso
Edited by the Electronicstalk Editorial
Team on 24 January 2008
Simulator answers reliability
requirements
Toshiba is using the Virtuoso UltraSim Full-Chip Simulator for quantitative simulation methodology for reliability analysis at 65nm and below
Toshiba has deployed Cadence Virtuoso simulation technology to provide its analogue and mixed-signal chip designers an easy-to-use and accurate reliability analysis flow Toshiba chose the Virtuoso UltraSim Full-Chip Simulator for quantitative simulation methodology for reliability analysis at 65nm and below to help ensure high performance and improve yield and quality of devices
This article was originally published on Electronicstalk on 26 May 2003 at 8.00am (UK)
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Toshiba and Cadence worked together to implement Toshiba's advanced reliability models into Virtuoso UltraSim simulator using the UltraSim Reliability Interface and tested the results, resulting in the selection of the UltraSim simulator.
"With the Cadence Virtuoso UltraSim, Toshiba can provide highly reliable ICs for our customers, who provide consumer electronics applications, telecom-related products and peripheral devices", says Masazumi Shiochi, Group Manager of Mixed Signal CMOS Design Group, Toshiba's Semiconductor Company.
"This reliability analysis flow enables us to meet our stringent reliability metrics, estimate the costs of test and debug, and meet our market window by providing high-quality devices to our end customers".
A part of Virtuoso Multi-Mode Simulation, the Virtuoso UltraSim Full-Chip Simulator is the Cadence FastSpice circuit simulator that provides performance, capacity and accuracy when verifying large custom, analogue mixed-signal, RF, memory and SoC designs.
It uses true hierarchical simulation with patented isomorphic, adaptive partitioning algorithms and accurate RC reductions technology to provide the capacity, accuracy, and performance required for full-chip transistor level verification, regardless of design type or stage in the design cycle.
"We worked closely with Toshiba to ensure their engineers had the reliability analysis technology they need to provide visibility into the quality of their most complex designs", says Sandeep Mehndiratta, Product Marketing Director at Cadence.
"The UltraSim Reliability Interface allows customers to plug in their proprietary model while securing their IP.
Toshiba was able to quickly implement the Virtuoso UltraSim reliability analysis in their flow, due to its ease of use and its ability to quantify the effect of performance and yield degradation for the lifecycle of their products".
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