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Design and Development Software
News Release from: Cadence Design Systems | Subject: QRC Extraction and Virtuoso Passive Component
Edited by the Electronicstalk Editorial
Team on 15 April 2008
RF design software is qualified at 65nm
Newly qualified technologies deliver tested and proven inductance, substrate extraction and passive component design.
Cadence Design Systems has received qualification of its QRC Extraction and Virtuoso Passive Component Designer packages for the TSMC 65nm process design kit The newly qualified technologies deliver tested and proven inductance, substrate extraction and passive component design
This article was originally published on Electronicstalk on 20 Nov 2001 at 8.00am (UK)
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Cadence QRC Extraction handles parasitic inductance and substrate extraction, while the newly released Virtuoso Passive Component Designer technology tackles inductor synthesis, analysis and modelling.
In June, Cadence and TSMC introduced a TSMC compatible 65nm RF PDK using the new Cadence Virtuoso custom design platform, and accompanying downloadable RF, analogue and mixed-signal (RF and AMS) design-flow demonstration packages for wireless designers.
The Cadence technologies were qualified as part of the new TSMC Electromagnetic (EM) Tool Qualification Programme, which targets TSMC 90 and 65nm process technologies.
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"Validation of Cadence technologies on our 65nm process node enables designers to build single-chip wireless applications by integrating RF transceivers and synthesisers on to the same SoC with digital baseband and application processors", says Tom Quan, Deputy Director of Design Service Marketing at TSMC.
Baseband circuits, microprocessors and memories move to the most advanced CMOS process node available.
To enable wireless system on chip, RF transceivers and frequency synthesisers must be implemented on the same process.
Using Cadence QRC Extraction signoff accurate modelling of the substrate and RLCK extraction of interconnects, RF designers can increase first-pass silicon success and reduce the cost of over design.
What-if analysis with noise contour maps enables designers to rapidly experiment with different placement alternatives of RF blocks in the vicinity of noisy digital circuits.
The TSMC 65nm PDK includes scalable inductor and transformer models validated with Virtuoso Passive Component Designer.
Model accuracy has been verified to be within a few% of measurements for inductance, quality factor and self-resonance frequency.
Designers are no longer confined to a limited set of PDK inductors.
Starting from design specifications such as inductance and quality factor, RF designers can create their own inductors and transformers in Passive Component Designer using scalable parameterised cells provided in the TSMC PDK.
The new technology reads TSMC 65nm rule files and synthesises components that are DRC- and LVS-clean and ready for Cadence QRC Extraction analysis.
The Virtuoso Passive Component Designer supports 65nm effects such as bias, erosion, metal fills and slotting.
"Cadence offers a complete RFIC design flow that combines system design, RF component design, circuit design, simulation, layout and physical verification", says Sandeep Mehndiratta, Product Marketing Director at Cadence.
"Cadence QRC Extraction now delivers the most comprehensive parasitic extraction, which includes accurate self and mutual inductances, as well as silicon-proven substrate effects extraction solutions - both critical for RF post-layout verification".
"Virtuoso Passive Component Designer enables designers to create custom inductors and transformers to meet their design specifications".
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