Verification IP products suit OVM users

The AMBA 3 AXI and AMBA AHB VIP are now available as multilanguage universal verification components (UVC) and are the first to provide OVM support within the Cadence VIP portfolio.

Cadence Design Systems' has released its first two testbench verification IP (VIP) products which are compliant with the Open Verification Methodology (OVM).

These enhancements enable the rapidly growing community of OVM users to easily access Cadence metric-driven verification solutions and to predictably achieve high-quality verification closure.

The AMBA 3 AXI and AMBA AHB VIP are now available as multilanguage universal verification components (UVC) and are the first to provide OVM support within the Cadence VIP portfolio.

OVM support will be added to the remaining protocols in the VIP portfolio in the second half of 2008.

Cadence VIP simplifies the overall verification development and integration process for design and verification teams that are developing OVM-based testbenches using an automated metric-driven approach.

Included with the VIP is the compliance management system (CMS), which automates compliance verification, one of the key benefits of the metric-driven approach.

CMS delivers high functional coverage with push-button ease, allowing users to avoid the most difficult aspects of protocol compliance verification.

The compliance management capability within the Cadence OVM verification IP reduces the necessary resources and expertise required to reach verification closure.

For example, the CMS aids in generating complex corner-case scenarios, eliminating most manual test writing.

This allows users to avoid the time-consuming and unpredictable aspects of using alternative VIP and improving quality, increasing productivity and delivering much higher levels of predictability.

"The Cadence metric-driven verification IP took only a few days to get up and running in our SystemVerilog testbench", said Suhas Belgal, Verification Manager of Magnum Semiconductor.

"The VIP significantly enhanced Magnum's ability to fully verify our designs that include both AHB master and slave ports".

The Cadence VIP provides much more than a simple bus functional model (BFM).

Cadence VIP includes the CMS, constrained-random stimuli generation, complete protocol checking, scoreboarding hooks and a full functional coverage solution.

Cadence VIP now addresses an even broader community of users with multilanguage testbench support for both SystemVerilog.

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