Product category:
Memory Devices and Modules
News Release from: Catalyst Semiconductor | Subject: SPI EEPROMs
Edited by the Electronicstalk Editorial
Team on 07 October 2002
Serial EEPROM family runs up to 256Kbit
Catalyst Semiconductor has completed qualification and released to production one of the most complete families of high-speed SPI interface serial EEPROMs in the industry.
Catalyst Semiconductor has completed qualification and released to production one of the most complete families of high-speed SPI interface serial EEPROMs in the industry "Market projections show that SPI interfaced EEPROMs should represent one quarter of the serial EEPROM market in 2005
This article was originally published on Electronicstalk on 7 Feb 2002 at 8.00am (UK)
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Catalyst Semiconductor has added two new digitally programmable potentiometer (DPP) ICs to its AE2 (analogue EEPROM) mixed-signal product line.
EEPROM provides more secure MPU supervision
Catalyst Semiconductor has expanded its AE2 analogue EEPROM mixed-signal product strategy with the CAT116x series of microprocessor supervisory circuits with serial 16Kbit EEPROM.
This represents a $325 million opportunity", says Catalyst Product Marketing Manager Gary Craig.
"The high speed serial SPI interface is preferred over parallel interfaces in applications where speed, board density and low costs are crucial.
Data communication and automotive applications are particularly well suited for SPI EEPROMs".
Catalyst's SPI family consists of 19 devices with memory density ranging from 1 to 256Kbit.
Speeds are 10MHz for all devices except the 128 and 256Kbit devices that operate at 5MHz.
Devices with standard 2bit block protection, enhanced 2bit block protection with software write protection and versatile 3bit block protection with software write protection are offered.
All four SPI clock/phase modes - 00, 01, 10 and 11 - are supported through factory programming options.
The new 3bit block write protection capability is available for 1 to 64Kbit density devices.
A status register with three block protection bits makes single-page write protection possible.
To write protect a small section of memory to hold, for example, a serial number or system ID, a large section of memory does not need to be locked.
Single-page write protection uses the memory array efficiently and is especially important with higher density memories.
The write protect enable bit, WPEN, within the device status register, allows software control of the memory array's write protection.
Write protection works with the hardware write protection pin to define which memory array segment is write protected.
In addition, by using the write protect pin and WPEN, a device can be made to appear one time writeable.
Details are given in Catalyst's Design Note 8, which is available from the company's website.
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